Effective Decap Insertion in Area-Array SoC Floorplan Design

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > journal & Dissertation > Item 987654321/31828

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/31828

Title:	Effective Decap Insertion in Area-Array SoC Floorplan Design
Authors:	Lu,Chao-Hung;Chen,Hung-Ming;Liu,Chien-Nan Jimmy
Contributors:	電機工程研究所
Date:	2008
Issue Date:	2010-07-06 18:12:26 (UTC+8)
Publisher:	中央大學
Abstract:	As VLSI technology enters the nanometer era, supply voltages continue to drop due to the reduction of power dissipation, but it makes power integrity problems even worse. Employing decoupling capacitances (decaps) in floorplan stage is a common approach t
Relation:	ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS??
Appears in Collections:	[Graduate Institute of Electrical Engineering] journal & Dissertation

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