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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/32080


    Title: Multilevel full-chip routing with testability and yield enhancement
    Authors: Li,Katherine Shu-Min;Chang,Yao-Wen;Lee,Chung-Len;Sul,Chauchin;Chen,Jwu E.
    Contributors: 電機工程研究所
    Keywords: ROUTER;DELAY
    Date: 2007
    Issue Date: 2010-07-06 18:18:09 (UTC+8)
    Publisher: 中央大學
    Abstract: We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. 1) The oscillation ring test (ORT) and its diagnosis scheme fo
    Relation: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
    Appears in Collections:[電機工程研究所] 期刊論文

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