A novel double-recessed 0.2-mu m T-gate process for heterostructure InGaP-InGaAs doped-channel FET fabrication

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Title:	A novel double-recessed 0.2-mu m T-gate process for heterostructure InGaP-InGaAs doped-channel FET fabrication
Authors:	Hwu,MJ;Chiu,HC;Yang,SC;Chan,YJ
Contributors:	電機工程研究所
Date:	2003
Issue Date:	2010-07-06 18:28:36 (UTC+8)
Publisher:	中央大學
Abstract:	A double-recessed T-gate process has been successfully developed to fabricate 0.2-mum gate-length heterostructure InGaP-InGaAs doped-channel FETs (DCFETs) to increase the gate-to-drain breakdown voltage. This technology uses direct electron-beam lithograp
Relation:	IEEE ELECTRON DEVICE LETTERS
Appears in Collections:	[Graduate Institute of Electrical Engineering] journal & Dissertation

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