本論文提出一個操作在1.25 GHz、擁有8個相位輸出並應用在低電壓操作的全數位式鎖相迴路。在此鎖相迴路中，使用多重相位數位控制振盪器因此可於低電壓時操作仍可獲高頻率輸出。此多重相位數位控制振盪器內含有多級次迴圈與環形延遲串列，可提升振盪頻率。於整體電路架構中，多重相位時間數位轉換器使用振盪器的多相位輸出對欲轉換之時間差值作取樣，此方法可大幅減少面積消耗。另外，在時間數位轉換器中使用時間放大器的技巧，增加轉換之時間解析度，進而減少量化雜訊的產生。 本論文之全數位式鎖相迴路使用TSMC 90 nm 1P9M CMOS製程實現晶片，其操作頻率範圍可從950 MHz到1.6 GHz，並且擁有8個相位的輸出。電路在操作電壓為0.6 V及操作頻率為1.25 GHz時，功率消耗為9.05 mW，而輸出訊號之最大峰對峰值時間抖動量為29.86 ps (3.73 %)，方均根抖動量為3.96 ps。整體晶片面積為456 × 456 um2，核心電路的面積為180 × 200 um2。This thesis presents an 1.25-GHz 8-phase all digital phase-locked loop (ADPLL) for low supply voltage applications. The ADPLL uses multistage sub-feedback loop and ring-based delay line (RB-DL) in the proposed multiphase digital controlled oscillator (MP-DCO) to obtain the higher operating frequency. A multiphase time-to-digital converter (MP-TDC) adopts the MP-DCO phase outputs to sample the timing difference. Therefore, the area of the TDC can be salved by this method. To reduce the quantization noise, a time amplifier (TA) can enhance the timing resolution of the TDC. The experimental chip of the proposed ADPLL was implemented by TSMC 90 nm 1P9M CMOS process. The measurement results show that the output frequency range is from 950 MHz to 1.6 GHz at 0.6 V supply voltage. The peak-to-peak jitter and RMS jitter of ADPLL are 29.86 ps and 3.96 ps at 1.25-GHz frequency, respectively. The power consumption is 9.05 mW at 1.25-GHz frequency and the chip area is 456 × 456 um2.
