可配置2×2,4×4,與8×8資料串流之K最佳多輸入輸出解碼器; Design of Configurable K-Best MIMO Detector for 2×2, 4×4, and 8×8 Data Streams

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題名:	可配置2×2,4×4,與8×8資料串流之K最佳多輸入輸出解碼器;Design of Configurable K-Best MIMO Detector for 2×2, 4×4, and 8×8 Data Streams
作者:	林世坤;Shih-kun Lin
貢獻者:	電機工程研究所
關鍵詞:	多輸入輸出解碼;可配置;離散K最佳演算法;連續干擾消除;MIMO detection;configurable;distributed K-best algorithm (DKB);successive interference canstellation (SIC);MIMO detection;configurable;distributed K-best algorithm (DKB);successive interference canstellation (SIC)
日期:	2010-12-10
上傳時間:	2011-06-04 16:13:36 (UTC+8)
出版者:	國立中央大學
摘要:	在此論文裡，我們提出了可適用於8×8、4×4 和 2×2不同的天線組態，以及可支援64-QAM、16-QAM和QPSK不同的調變方法且K值可支援10和5的K最佳多輸入輸出解碼器。我們的設計運用了離散K最佳演算法(Distributed K-best, DKB)來減少傳統K最佳演算法每層的拜訪點從K√M到2K-1點，為了進一步減少拜訪的點數，又使用了連續干擾消除(Successive Inference Constellation, SIC)取代某些特定層數的DKB。在硬體的實現上，我們利用DKB與SIC的組合方塊來達到管線式架構可配置的需求。為了減少乘法器的複雜度，我們使用移位乘法器(Shift Multiplier, SM)來取代傳統的乘法器。本論文使用SMIMS VeriEnterprise Xilinx FPGA驗證電路功能，最後利用90-nm CMOS製程來實現所提出的可配置的多輸入輸出解碼器。該晶片核心面積為0.877×0.877mm2，當晶片操作在78.12 MHz以及1V的供應電壓和8×8 64QAM K=10的模式時其功率消耗僅16.5mW。 In this thesis, we proposed a MIMO detector which can support multiple antenna types (8×8, 4×4, and 2×2), various modulation schemes (64-QAM, 16-QAM, and QPSK) and two K-values (K=10 or K=5) for IEEE 802.16m standard. From the algorithm aspects, the adopted distributed K-best (DKB) algorithm can reduce the number of visited nodes at each layer from K√M to 2K-1, compared with the conventional K-best algorithm. To further reduce number of visited nodes, our design employs successive inference cancellation (SIC) in some specific layers to replace the DKB layer. In terms of hardware implementation, the DKB and SIC are designed as elementary building blocks. With these building blocks, the proposed MIMO detector can flexibly achieve the configurable architecture. In order to simplify the multiplier complexity, we propose a novel shift-multiplier (SM) to replace the conventional multiplier. The proposed configurable MIMO detector is verified by the SIMIS VeriEnterprise Xilinx FPGA development board. Finally, this design is fabricated in a 90-nm CMOS technology. The core area is 0.877 0.877 mm2. With the 1V supply voltage, the chip power is 16.5 mW in 8×8 64-QAM mode and its clock rate is 78.12 MHz.
顯示於類別:	[電機工程研究所] 博碩士論文

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