本論文利用0.18 ?m CMOS標準製程來實現矽光檢器，此光檢器主要由N/P-implant、N/P-well及Deep-N-Well所構成，其中Deep-N-Well另給偏壓的設計是為了排除大量基板慢速載子，此設計無論透過MEDICI二維元件模擬軟體亦或實際下線晶片的量測皆證明光檢測器頻寬的有效提升；其量測到的3-dB頻寬在元件同樣操作於N bias(反偏)為11.83 V情況下，可從未給DNW bias (即floating)時的200 MHz，提升至DNW bias為0 V時的2.69 GHz，同時其頻寬增益乘積為347.80 GHz，並且透過適當偏壓的調整可於N bias為11.50 V時達到最佳頻寬5.77 GHz。 而DNW另給偏壓的光檢測器架構雖能藉排除基板載子來提升頻寬，卻也因此使得響應度過低，如前述結構操作在最佳頻寬時5.77 GHz時，其響應度僅0.019 A/W。而本論文最後提出的結構即利用不同偏壓方式的設計，能有效收集在PD操作區中p-substrate照光產生的載子，明顯地提升了元件的響應度，其最佳的響應度於P bias為 -11.83 V時達到1.17 A/W，同時3-dB頻寬為1.9 GHz，達到較佳的頻寬與響應度乘積。 This work demonstrates photodetectors (PDs) fabricated by standard 0.18 ?m CMOS technology. In the proposed PD structure with Deep-N-Well layer, we show a obvious improvement when DNW bias is added. At reverse bias 11.83 V, the 3-dB bandwidth improve from 200 MHz to 2.69 GHz when the DNW bias vary from floating to 0 V. The reason may be the removal of slow diffusive carriers which are generated from substrate. We also observe that the 3-dB bandwidth of our PDs will be better when the reverse bias get slightly decreased in the avalanche region. At reverse bias 11.50 V, the 3-dB bandwidth can achieve 5.77 GHz when DNW bias is 0 V. The possible reason may be the decrease of avalanche delay time. However, when we consider the speed and gain in the same time, the best bias condition is 11.83 V, which yield a gain-bandwidth product of 347.80 GHz. Finally, a new photodetector with high responsivity has been demonstrated. The photodetector is biased by p-implant rather than n-implant in the previous design, and DNW layer is grounded with n-implant inside the PD. From both simulation and measurement result, the responsivity increase since the effective collection of hole generated inside the p-type susbrate in the operation region. The responsivity achieves 1.17 A/W, with 3-dB bandwidth of 1.9 GHz in the same time.
