本論文的主要研究內容為利用可調式匹配網路於功率放大器效率之提升。我們使用變容二極體與電晶體開關設計可調式匹配網路，以改變電晶體的負載阻抗，提升功率放大器於低功率區時的效率。 首先，我們使用WIN 0.15-μm GaAs pHEMT製程中的變容二極體作為可調式元件來設計一負載阻抗連續可調之功率放大器。在頻率5.8 GHz下的量測結果顯示，其Pout,1dB為20.8 dBm。與製作於同一晶片上之固定式功率放大器比較，當輸出功率為18.5 dBm時，可提升2.8% 之PAE，並降低12% 的直流功率消耗。 接著，我們使用以TSMC 0.18-μm SiGe BiCMOS製程中的CMOS電晶體開關來實現可切換式功率放大器。在頻率6.4 GHz下的量測結果顯示，當輸出功率為17 dBm時（約4-dB back-off），將CMOS開關由ON-state切換為OFF-state，可提升3.3% 之PAE，並降低22% 的直流功率消耗。 本論文設計使用可調式匹配網路之功率放大器，並成功將之以積體電路製程實現。由量測結果得知此可變負載技術的確可以有效地提升功率放大器之效率，並顯著地降低其直流功率消耗。 The focus of this thesis is to use tunable matching networks for power amplifier efficiency enhancement. We design varactor-based and switch-based tunable matching networks to vary the load impedances presented to the transistors in order to enhance the power efficiency of the power amplifiers in low power regions. First, a power amplifier with continuously tunable load impedance is designed based on the varactors on WIN 0.15-μm GaAs pHEMT process. The measurement results at 5.8 GHz show that the P1dB of the power amplifier is 20.8 dBm. Compared with a power amplifier with fixed matching network that is fabricated on the same chip, the tunable power amplifier exhibits a PAE enhancement of 2.8% and a 12% reduction in DC power consumption at the output power level of 18.5 dBm. Next, a swichable power amplifier is realized using the CMOS switches in TSMC 0.18-μm SiGe BiCMOS technology. The measurement results at 6.4 GHz show that, when the switch is switched from ON state to OFF state, the PAE is enhanced by 3.3% whereas the DC power consumption is reduced by 22% at the output power level of 17 dBm, which corresponds to 4-dB power back-off. In this thesis, power amplifiers with tunable matching networks are designed and successfully implemented using integrated circuit technologies. Verfied by measurement results, the variable load technique can effectively enhanece the power efficiency and significantly reduce the DC power consumption of the power amplfiers.
