Proposed is a dynamic frequency tracking and phase error compensation clock de-skew buffer (CDSB) to reduce the clock skew between the input and output clocks of a chip. The proposed CDSB tracks the dynamic frequency in two clock cycles. Also, the CDSB utilises a fine tune circuit which is based on a cyclic rotation algorithm to compensate for the dynamic phase error. Measured results show that the operating frequencies of the CDSB are from 200 to 450 MHz. Also, the CDSB tracks the dynamic frequency in two clock cycles. The power consumption, RMS jitter, and peak-to-peak jitter of the CDSB are 9.71 mW, 2.7 ps, and 31.3 ps at 450 MHz.