在下世代的行動通訊系統中，3GPP LTE/LTE-Advanced為目前世界上行動通訊的主要規格之一，主要採用正交分頻多工存取調變，對於高頻選擇性衰減通道有著較強的抵抗力。所以本論文以LTE的規格，並搭配多輸入多輸出技術，來實作接收機。在接收機通能區塊上，大致可分為兩個部分。同步錯誤追蹤部分，使用2對參考訊號來估測殘餘的載波頻率偏移，另一部分為通道變化的追蹤，主要利用可適性RLS來追蹤時間方向內插器的係數。在硬體設計上面，採用下列技術來降低硬體複雜度。利用排程將讀寫的時間錯開，減少記憶體使用的埠數，也可減少記憶體的使用量，來降低硬體消耗。在可適性RLS方面，運用排程來解決因為加入管線級暫存器而造成的係數更新問題，並設立係數更新機制，防止有限精度造成量化錯誤在遞迴過程累積使係數發散。整個接收機在車速240 km/hr的環境下有良好的表現，我們更嘗試支援到360 km/hr，並加入多輸入多輸出來增加throughput。而整個接收機有透過FPGA做驗證，而通道追蹤的部分，更有透過CIC下線，做出晶片驗證。晶片大小2.46 × 2.46 mm2，使用CQFP144封裝，core gate count 1023K，最大頻率為100 MHz，throughtput最高達到497.75 Mbps。LTE/LTE-Advance is one of the main standards for the next-generation mobile communication system. It uses OFDMA for modulation, which has better resistance to highly frequency-selective fading channels. In this thesis, a baseband receiver that follows the parameters of LTE/LTE-A and incorporates the MIMO conficuration is designed.Two essential functional blocks are considered in the receiver. The first part is related with synchronization. Two pairs of reference signals are used to estimate the residual synchronization errors. The other part is designed for tracking channel variation under high mobility. It uses adaptive RLS algorithm to accelerate convergence of the filter coefficents.As to the hardware design, we propose some techniques to reduce the complexity. The data-paths are well-scheduled so that non-comflict memory access can be accomplished with reduced memory I/O ports, and memory sizes. For the implementation of the adaptive RLS algorithm, the RLS updating procedureis also re-scheduled to solve the problem caused by insertion of pipeline registers. Furthermore, a novel reset mechanism is designed to prevent the divergence resulted from the quantization error accumulation due to finite precision effect in the iterative loops.The receiver is verified to have satisfying performance under mobility of 240 km/hr, and even up to 360 km/hr. In the end, we verify the receiver on the FPGA platform. The block of channel tracking engine is taped out through CIC. The chip size is 2.46 × 2.46 mm2, and the pakage is CQFP144. The gate count is 1023K, and from post-layout simulation, the max frequency achieves 100 MHz, and the throughput is 497.75 Mbps.
