應用於UWB/V頻段寬頻CMOS低雜訊放大器之研究;The Design and Implementationof Wideband CMOS Low Noise Amplifier for UWB and V-Band Applications

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题名:	應用於UWB/V頻段寬頻CMOS低雜訊放大器之研究;The Design and Implementationof Wideband CMOS Low Noise Amplifier for UWB and V-Band Applications
作者:	陳欣瑋;Chen,Shin-Wei
贡献者:	電機工程研究所
关键词:	寬頻;低功耗;低雜訊放大器;LNA;UWB;wideband;low power;V-band
日期:	2012-07-20
上传时间:	2012-09-11 18:52:48 (UTC+8)
出版者:	國立中央大學
摘要:	本論文題目為應用於UWB / V頻段之寬頻CMOS低雜訊放大器之研究，文中主要在探討低雜訊放大器的寬頻跟低功耗的設計方式，文中主要提出了四個主要實現寬頻特性的不同電路。第一個電路為應用於UWB寬頻自偏壓低功耗之低雜訊放大器，本電路的重點在於如何在應用範圍(3~5 GHz)內有效提升頻寬、增益和降低功耗，設計方式為透過電晶體和電阻回授可以有效提升基本頻寬，使用峰值電感可以再提升高頻的增益和降低頻帶內的雜訊而此方式的目的在於共振掉寄生電容，由於回授會降低增益，因此使用轉導增強型疊接架構可以使用較低的電流來達到較高的轉導能力，透過電流鏡在輸出和輸入的連接，此電路的偏壓方式為自我偏壓，透過決定輸出端的偏壓條件可以使整體電路在最低的功耗值達到最好的特性，電路量測結果在DC ~ 4.8 GHz時增益最大有13.9 dB，輸入與輸出反射係數分別為-20.2 dB 及-17.5 dB，雜訊指數為2.78 dB，輸入三階交互調變交叉點為-14 dBm，電路功率消耗為10.45 mW，晶片面積為0.462 mm2。本電路採用tsmc^TM 0.18 μm 製程。第二個電路為應用於UWB寬頻自偏壓低功耗之低雜訊放大器，本電路的重點在於如何在應用範圍(3.1~10.6 GHz)內有效提升頻寬、增益和降低功耗，設計方式使用電阻回授來實現基本頻寬，由於電晶體的米勒效應的存在，故在汲極端加上了一電感來共振掉寄生電容，因此整體頻寬可達到12 GHz左右，由於回授的關係會使增益降低，因此再加入一個共源級以提升增益，使用了PMOS當負載，因此整體電路達成自我偏壓特性，量測結果在2 - 13 GHz時增益最高有13.9 dB，輸入與輸出反射係數分別為-14 dB 及-19 dB，雜訊指數為3.6 dB，輸入三階交互調變交叉點為-4.8 dBm，電路功率消耗為11 mW，晶片面積為0.574 mm2。本電路採用tsmc^TM 0.18 μm 製程。第三個電路為應用於V頻段寬頻低雜訊放大器，本電路的重點在於如何在應用範圍(57~64 GHz)內有效提升頻寬、增益。設計方式為因為要實現寬頻輸入輸出，在單級疊接架構上的所有匹配網路皆使用了低品質因數之設計，透過此設計可以有效提升頻寬，爾後，再透過三級單級疊接架構串接，即可在應用範圍達成效果，而由於受限在電晶體本身在此頻段的高雜訊，而在疊接架構中加上一電感以使得雜訊在輸出端的放大能力可以降至最低。電路量測結果在50 - 59 GHz時增益最高有10.9 dB，輸入與輸出反射係數分別為-17.9 dB 及-9.8 dB，雜訊指數為6.4 dB，輸入三階交互調變交叉點為+0.7 dBm，電路功率消耗為35 mW，晶片面積為0.706 mm2。本電路採用tsmc^TM 90 nm 製程。第四個電路為應用於V頻段寬頻低功耗之低雜訊放大器，本電路的重點在於如何在應用範圍(57~64 GHz)內有效提升頻寬和降低功耗，在直流偏壓方面，設計方式為先訂出可以實現的直流功耗，透過單級電流最大的流量規範，在已選定的尺寸下找出最佳的最大可用增益和雜訊最低值，再透過增益和雜訊的比較下以此方式來得到最低功耗、最好的增益和最低的雜訊，在寬頻實現方面則是採用低品質因數的匹配網路。電路量測結果在45-57 GHz時增益最高有11.8 dB，輸入與輸出反射係數分別為-14 dB 及-23 dB，雜訊指數為5.7 dB，輸入三階交互調變交叉點為-9.5 dBm，電路功率消耗為13.5 mW，晶片面積為0.525 mm2。本電路採用tsmc^TM 90 nm 製程。The title of this thesis is “The Design and Implementation of Wideband CMOS Low Noise Amplifier for UWB and V-Band Applications”, in this thesis, we study the design of wideband and low power realization used in low noise amplifier and finally, we bring up four different circuit with wideband technique.The first circuit is “A Low-Power Wideband Self-Biased Low Noise Amplifier for UWB Receiver Front-End”, the emphasis of this circuit is how to boost gain、bandwidth and reduce power consumption, and the way is that we can boost the normal bandwidth effectively by the way of MOSFET and resistor feedback, the purpose of inductive-peaking is series resonate with parasitic capacitor and by this way, the gain-boosting and noise reduction can be realization. Because of the low gain of feedback, the Gm- enhancement CASCODE is used and the reason is that we can acquire the higher transconductance by the current-reuse topology. Through the connection of current-mirror at the input and output stage, the bias of this circuit is total self-biased, by the condition of bias at output, the lowest power consumption of this circuit can be taken via this consideration. This LNA achieved a measured gain of 13.9 dB from DC to 4.8 GHz. The input and output return is 20.2 dB and 17.5 dB, respectively. The measured NF is 2.78 dB and IIP3 is -14dBm. The power consumption is totally 10.45 mW. The chip area is 0.462 mm2. Finally, this circuit is processed by tsmc^TM 0.18 μm CMOS process.The second circuit is“A Low-Power Wideband Self-Biased Low Noise Amplifier For 3.1-10.6 GHz application”, the emphasis of this circuit is how to boost gain、bandwidth and reduce power consumption in 3.1-10.6 GHz, and the way is that we use resistor feedback to realize normal bandwidth, because of the miller effect, we add a inductor at Drain in order to resonate parasitic capacitor, therefore, we can get the bandwidth about 12 GHz. The final stage is a common-source topology. PMOS as a active load is used, then, the properties of bias is self-biased. This LNA achieved a measured gain of 13.9 dB from 2 to 13 GHz. The input and output return is 14 dB and 19 dB, respectively. The measured NF is 3.6 dB and IIP3 is -4.8dBm. The power consumption is totally 11 mW. The chip area is 0.574 mm2. Finally, this circuit is processed by tsmc^TM 0.18 μm CMOS process.The third circuit is “A Wideband V-Band Low Nosie Amplifier”, the emphasis of this circuit is to boost gain、bandwidth, and the way is that we realize wideband input and output matching, in a sigle common-source architecture, all the matching network including inter-stage is low Q type, bandwidth can be boosted effectively through this way. Next, through the CASCADE of 3-stages CASODE, the properties of wideband is achieved in application. In the limit of high noise of MOSFET at V-Band, we add a inductor in CASCODE, therefore, the noise generated from gate can be limited. This LNA achieved a measured gain of 10.9 dB from 50 to 59 GHz. The input and output return is 17.9 dB and 9.8 dB, respectively. The measured NF is 6.4 dB and IIP3 is +0.7 dBm. The power consumption is totally 35 mW. The chip area is 0.706 mm2. Finally, this circuit is processed by tsmc^TM 90 μm CMOS process.The fourth circuit is “A V-Band Wideband Low Power Low Nosie Amplifier” the emphasis of this circuit is how to boost bandwidth and reduce power consumption, and the way is that we set up the power consumption, and then calculate the maximum current flow though a single common-source, under the selected size, we can get the best performance of MAG and NFmin. This LNA achieved a measured gain of 11.8 dB from 45 to 57 GHz. The input and output return is 14 dB and 23 dB, respectively. The measured NF is 5.7 dB and IIP3 is -9.5 dBm. The power consumption is totally 13.5 mW. The chip area is 0.525 mm2. Finally, this circuit is processed by tsmc^TM 90 μm CMOS process.
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