為了縮短類比積體電路的設計時間，類比積體電路的自動化設計，也慢慢的受到重視。然而，由於深次微米效應的影響，在方程式基礎的方法中對於電晶體參數的預估往往存在很大的誤差，這造成了電路效能的預估不夠精確，因此需要數個迴圈重覆修正，而本論文便是採用gm/ID的概念來解決此問題。由於gm/ID與電晶體大小無關，因此只需要使用偏壓及電流作為變數，便能夠精確地預估電路的效能，在整體設計的效率及精確度都有很大的改善。除此之外，本論文加入了寄生效應的考量來增加預估電路效能的精確度，每顆電晶體的通道長度也變成能讓使用者自行決定的變數。整個自動化流程以MATLAB實現，從實驗結果可看出整體的低頻增益、相位邊限以及單一增益頻寬皆得到較小的誤差值。另外，由於通道長度為可變動之參數，故最後設計出來的電路面積也能較先前的方法所得到的設計來的小。In order to shorten the design cycles of analog circuits, analog design automation has become a popular research topic. However, due to the deep-submicron effects, the estimated transistor parameter often exist errors in the equation-based approaches. This results in wrong prediction of circuit performance and leads to several redesign cycles to meet the specifications. In this thesis, the gm/ID design concept is adopted to solve this problem. Because gm/ID is an independent value to the device size, only internal bias voltages and currents are required to predict circuit performance, which greatly improves the overall efficiency and accuracy.In addition, this thesis also considers the parasitic effects to improve the accuracy of estimating the circuit performance. The channel length of each transistor also becomes a flexible variable to provide more choices to users. The entire automation process has been implemented in MATLAB environment. According to the experimental results, the prediction errors of overall low-frequency gain, phase margin and unity gain bandwidth are successfully reduced. In addition, because the channel length of some transistors can be adjusted, the circuit areas are smaller than the designs generated in previous approach.
