改善功率承受能力之微波/毫米波開關電路;Improved Power Handling Capability of Microwave/Millimeter Wave Switch Circuit

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题名:	改善功率承受能力之微波/毫米波開關電路;Improved Power Handling Capability of Microwave/Millimeter Wave Switch Circuit
作者:	胡詠昕;Hu,Yong-xin
贡献者:	電機工程研究所
关键词:	寬頻開關電路;功率承受能力;插入損失;開關電路;broadband switch circuit;power handling capability;insertion loss;switch circuit
日期:	2012-08-29
上传时间:	2012-09-11 18:55:53 (UTC+8)
出版者:	國立中央大學
摘要:	本論文以CMOS製程來實現微波開關電路的設計，主要是因為跟三五族製程比較起來，CMOS製程擁有低成本及高度整合性的優點，且製程的技術逐漸進步，可以藉此設計出高頻或者是高功率的電路。但是設計高功率開關電路的難處在於CMOS製程材料本身的崩潰電壓較低，且使用的基板為低阻值基板，這會使得電晶體本身的寄生電容增加，而影響到開關電路的特性。為了能夠提升開關電路的特性，使用了在基底、Deep N-well及基板給予適當偏壓的技術來改善開關電路的功率承受能力。首先，以CMOS製程設計出1.9 GHz高功率開關電路，其功率承受能力可以達到36 dBm，但是其插入損失大於3 dB。因此，為了能有所改善插入損失，於是把電晶體串聯的數目及尺寸加以減少，來降低電晶體本身的寄生電容。發射端電路的插入損失在1.9 GHz下，可改善至1.9 dB，功率承受能力可以達到34 dBm。此外利用90 nm CMOS製程設計出寬頻(20 – 70 GHz)的開關電路，此電路使用雙閘極電晶體來改善開關電路的功率承受能力及切換速度。在30 GHz下，功率承受能力達到19 dBm，開關電路的切換速度可以達到10 Gbps。最後則是以氮化鎵製程來實現高功率開關電路的設計，使用傳統的串並式架構，藉由電感與電晶體本身的寄生電容達成匹配的效果。其功率承受能力在2 GHz下，輸入功率達到35.5 dBm時，為1 dB壓縮點。Standard CMOS technology was used to design microwave switch circuits in this thesis. The main reason is that CMOS technology demonstrates some advantages, such as low cost and high integration capability, while compared with Ⅲ-Ⅴ semiconductor technology. The advance of CMOS technology can be used for high-frequency or high-power application. However, it is hard to design high-power switch circuits due to the low breakdown voltage of CMOS. The low resistance of silicon substrate increases the parasitic capacitance of transistor and degrades the switch circuit performance. In order to improve power handling capability of switch circuit, a new bias methodology in body/Deep N-well/substrate, has been proposed in this thesis. In the beginning, a high power CMOS switch operated at 1.9 GHz was presented with the measured P1dB compression point of 36 dBm but insertion loss of > 3 dB was achieved. Therefore, a revised CMOS switch with decreased transistor numbers in series sub-circuit and scaled down transistor size to decrease parasitic capacitance of transistor and thus improve insertion loss was proposed. When parasitic capacitance was decreased, the insertion loss was improved. So, insertion loss of transmit mode was improved to 1.9 dB and power handling capability remained 34 dBm at 1.9 GHz.Moreover, a wideband switch design (20 – 70 GHz) in 90 nm CMOS technology using dual-gate transistors was proposed. The power handling of 19 dBm and switching rate of 10 Gbps was observed at 30 GHz.Finally, a high power switch circuit design based on GaN process was designed and fabricated. The conventional series-shunt structure and matching network technique were used in this high power GaN switch. The power handling of 35.5 dBm was measured at 2 GHz.
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