| 摘要: | 隨著高速數位電路及記憶體相關電路的操作頻率上升，時脈的扭曲(Skew)愈易造成系統的誤動作。要解決時脈扭曲的問題，時脈同步電路如鎖相迴路(Phase-Locked Loop, PLL)、延遲迴路(Delay-Locked Loop, DLL)及同步複製延遲電路(Synchronous Mirror Delay, SMD)等，便被提出來校正時脈的相位或頻率。而除了同步問題外，時脈扭曲造成的責任週期(Duty cycle)變動，也是需要校正以確保電路操作的可靠度，而脈波寬度控制迴路(Pulse-Width Control Loop, PWCL)便是最常被拿來應用的。在傳統的脈波寬度控制迴路中，向來存在著較大的迴路濾波器面積以及對製程、電壓及溫度(PVT)變異的敏感度問題。在本論文中提出以全數位方法實現的脈波寬度控制電路，除了可克服上述缺點外，由於可程式化的優點，更可提高在系統上應用的可行性。在本論文中，為了增加輸入訊號的可操作頻率以及可操作責任週期的範圍，使用了脈波產生器和頻率偵測器來自動調校出具適當脈波寬度的時脈，以確保訊號順利於可控延遲線中傳遞。首先在控制機制部分，本論文採用了5位元的時間數位轉換器和4位元的逐漸近似暫存器作為相位控制的粗調以及細調機制。透過控制機制使得複製可控延遲線落後可控延遲線一個週期的時間差，利用多工器選擇兩條延遲線的多相位輸出訊號，則此二個被選擇的訊號間的相位差即可透過SR閂鎖器(SR-latch)轉為輸出訊號的責任週期。最後在訊號輸出前，利用一個簡單的同步複製延遲電路對進入SR閂鎖器前的訊號進行同步的功能，如此便可在訊號輸出時具有與輸入訊號相位同步的功能。本作的輸出訊號責任週期可控範圍為30 ~ 70%，以每10%作為單位，最高操作頻率為1.6 GHz，在模擬上的抖動為8.8 ps，面積為0.076 mm2。操作在輸入頻率為1.6 GHz 供應電壓為1.2 V時，功率消耗約為26 mW。With the raising of operation frequency in system-on-a-chip (SoC), clock skew becomes a more important issue needed to be solved. Phase-locked loop (PLL), delay-locked loop (DLL), and synchronous mirror delay (SMD) are used to deskew clock skew in phase and frequency. Except phase alignment, duty cycle distortion is needed to calibrate for system reliability. And pulse-width control loop (PWCL) stands to suppress clock skew on duty cycle. This study proposes a 0.8 ~ 1.6 GHz all-digital synchronous pulse-width control loop in a 90-nm CMOS process. Forsaking the conventional analog PWCL being the enormous filter area cost as well as sensitive to the process, voltage, and temperature (PVT) variations, the all-digital PWCL mitigates such issue, and exhibits the digital implementation for the compact size. By doing so, it is desirable to be used for the relative clock generation to calibrate the clock duty in the SoC and DDR applications. With regard to the wide operating frequency range and duty cycle of the input clock, the proposed all-digital PWCL uses the pulse generator (PG) and frequency detector (FD) to automatically adjust the appropriate pulse width of the clock, conforming to the successful clock transmission through the variable delay line (VDL) under PVT variations. In addition, based on the 5-bit time-to-digital (TDC) and 4-bit successive approximation register (SAR) architecture for the coarse and fine phase locking, respectively, the output phase of VDL aligns to that of replica VDL (RVDL).Thus, the phase difference between VDL’s and RVDL’s tenth phase output would be the one clock period. Thus, when one of VDL and RVDL stage phases is selected by the following MUX, the phase spacing between two clocks could be similar to the pulse width of the period signal. As a result, through the synchronous mirror delay (SMD) synchronizing the external clock input signal, the SR-latch combines two phase-delayed signals, and the available duty cycle is generated. The proposed all-digital PWCL generates the output clock with the duty cycle of 30 ~ 70 % in steps of 10%. Operating at 1.6 GHz clock rate, the simulated peak-to-peak jitter is 8.8 ps. The chip area occupies 0.076 mm2, and the total power consumption is around 26 mW at supply of 1.2V. |
