| 摘要: | 現今微電子構裝系統中，為容納更高密度的I/O（Input/Output）數目在高階IC晶片上，覆晶接點(flip-chip bumps)尺寸將大幅縮小至50 μm以下。如此，每個覆晶接點所承受的電流密度將會高達104 A/cm2或更高，進而造成電遷移效應誘發失效行為(electromigration-induced failure)，此失效行為將嚴重IC晶片內覆晶接點之可靠度。因此，在此碩士論文中，於第三章，我們先利用一個基本的覆晶式銅/錫/銅銲點結構去探討錫原子逆迴流通量(JSn,back-filled)存在的成因以及銅箔消耗陰極介金屬消耗的演進過程，另外，我們也利用一特殊的T字形結構，設計出一嶄新的方式計算銅原子在銅錫介金屬中的有效碰撞係數(effective charge number, Z*Cu/Cu6Sn5)。 在第四章中，得到這些參數後，我們可以定量出電遷移誘發錫在錫的電遷移原子通量(JSn,EM)和錫原子逆迴流通量(JSn,back-filled.)。一旦，得到以上兩個錫原子通量，我們可以修改學長的陰極界面電遷移失效行為圖，於錫孔洞形成的區域，再增加此二通量的影響，去定義出嶄新的陰極界面電遷移失效行為圖。將(JSn,EM)和(JSn,back-filled.).做相等可以取得固定電流密度下的臨界溫度值(Tcrit.)，再利用這些臨界溫度值去修改出陰極銅/錫界面電遷移誘發失效圖。 最後，我們建構出更可靠與正確的陰極界面電遷移失效行為圖。
Due to the number of the I/O (input/outout) counts in the advanced IC will continue to increase quickly
the diameter of flip-chip bumps will approach to 50 μm and below. The current density in each flip-chip bumps could reach 104 Amp/cm2 or higher. While the high density of current flowing through the flip-chip solder bumps, EM (electromigration)-induced failure has become a serious reliability issues for the solder joint. Hence, in this work, we will first propose a innovated concept of Sn back-filled phenomenon, and we will use this Sn back-filled flux (JSn,back-filled). Also, a new method of calculating Z* value of Cu in Cu6Sn5 has been proposed in Chapter 3. In Chapter 4, the entire EM-induced failure modes at the cathode Cu/Sn solder joint interface would be discussed in a great detail. In Chapter 4, we will introduce how to calculate the Sn back-filled flux (JSn,back-filled), and the Sn EM flux (JSn,EM). By knowing this two Sn back-filled flux (JSn,back-filled) and the Sn EM flux (JSn,EM), we can
modify the failure map constructed by Hua Wei. By equaling the JSn,back-filled and the JSn,EM, we can obtain the a critical temperature (Tcrit.) at a constant current density. Then, we can use various critical temperatures to plot a EM-induced failure map at the cathode Cu/Sn interface under EM effect. Finally, based on the concept of Sn back-filled flux and Sn EM flux, we can construct a more reliable and accurate plot of the EM failure behavior at the cathode Cu/Sn interface. |
