用於三維積體電路矽穿孔之內建測試與量測技術; Built-In Test and Measurement Techniques for Through-Silicon Vias of 3D ICs

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题名:	用於三維積體電路矽穿孔之內建測試與量測技術;Built-In Test and Measurement Techniques for Through-Silicon Vias of 3D ICs
作者:	巫函諭;Wu,Han-yu
贡献者:	電機工程學系
关键词:	三維積體電路;矽穿孔;內建自我測試;延遲時間量測;內建自我量測;TSV;3D IC;delay measurement;BIST;BIDM
日期:	2013-07-24
上传时间:	2013-08-22 12:12:58 (UTC+8)
出版者:	國立中央大學
摘要:	使用穿矽穿孔 (TSV) 的三維整合技術是目前新興的電路設計技術。三維積體電路利用矽穿孔將多層裸晶進行堆疊，就一般製造三維積體電路而言可以分為兩個步驟：矽穿孔的成形與製造以及裸晶的堆疊。無論是在矽穿孔的製造或是堆疊過程中都會產生新的錯誤機制，如何有效測診斷與修復提高矽穿孔與整體三維積體電路良率是非常重要的。本論文中第一部分針對電源與訊號矽穿孔提出一測試與診斷技術，可以有效將矽穿孔中的電阻性開路與短路進行判別。提出的方法中針對電阻性開路可以達到100 歐姆而短路部分可以達到40K 歐姆的精準度。本篇論文第二部分，我們提出了一個矽穿孔內建延遲時間量測電路(BIDM)去量測矽穿孔本身造成的傳遞延遲時間。這部份我們同時實作了晶片去驗證我們提出的內建自我量測電路功能。經由量測結果可以觀察出BIDM 提供了18ps 的精準度，並且相較傳統游標尺量測電路我們提出的改良電路可以減少18%的面積成本。最後在本篇論文中我們將利用前面所提出的測試與量測方法進行兩種應用。利用矽穿孔測試方法提升整體電源矽穿孔良率，以及BIDM 的量測結果搭配可程式化緩衝器達到低功耗設計。由實驗結果可以發現當冗餘電源矽穿孔可以有效提升整體電源網絡的良率。另外在功耗分析中可以發現訊號矽穿孔的功耗藉由調整適當緩衝器驅動能力可以有效降低功率消耗並保持一定的時間限制。 Three-dimensional (3D) integration technology using through-silicon via (TSV) is one emerging integrated circuit (IC) technology. A 3D IC consists of multiple dies vertically connected by TSVs. The manufacturing process of a 3D IC can be roughly divided into two phases: die manufacturing including TSV forming and die stacking. Either the TSV forming or the die stacking may induce new failure mechanisms in the TSVs. Effective test, diagnosis and repair techniques for TSVs thus are imperative for ensuring the quality and yield of the 3D ICs. In the first part of this thesis, we propose a test and diagnosis scheme for power and signal TSVs. In addition to the testing of TSVs, the proposed diagnosis method can distinguish the resistive open faults from short faults of TSVs. It can detect open defect which resistance is larger than 100? and short defect which resistance is larger than 40K?. In the second part of this thesis, we propose a built-in delay measurement (BIDM) method to measure the propagation delay through the signal TSVs. Also, the test chip is implemented to demonstrate the BIDM function. The proposed BIDM has the feature of high accuracy and low area cost. The measurement results of test chip show that the resolution of BIDM can reach 18ps. In comparison with a typical Vernier delay line, the proposed BIDM can achieve 18% area cost reduction. In the third part of this thesis, we introduce two applications of the proposed test method and BIDM for enhancing the yield power TSVs and minimizing the power consumption of signal TSVs. Simulation results show that the yield of power TSVs in the power delivery network can be improved by redundant power TSVs. Power analysis also shows that the power consumption of signal TSVs can be reduced by tuning the drivingcapability of programmable driver of TSVs when the number of the stacked dies not as many as expected, and delay time of TSVs still satisfies timing constraint.
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