近年來，MIMO (Multi-Input Multi-Output,多輸入多輸出)系統越來越受到重 視，不僅因為多天線技術能夠有效的增加系統的吞吐率，應用多天線的技巧也能 提升系統的效能，但也必須處理各種傳輸端對接收端之天線數目不同所帶來的問 題，本論文以波束成型(Beamforming)常用的預編碼技巧SVD (Singular Value Decomposition, 奇異值分解)之硬體實現為目標，設計一可支援1 × 1~4 × 4之任 意天線組合之SVD 處理器，為了減少傳統Memory-Based 架構所必須增加的時 序延遲，我們使用一暫存器陣列來取代實際的記憶體，並且設計一能夠配合演算 法做管線化的架構做硬體實現，所提出之設計除了能夠對應任意天線組合之外， 在面積、運算時間與功率消耗上也有相當的改善。本論文以SMIMS VeriEnterprise Xilinx FPGA 驗證電路功能，最後利用TSMC-90nm 製程實現所設計之電路。 In recent years, it is more important to use MIMO (Multi-Input Multi-Output) systems. MIMO techniques not only increase system throughput but also improve system performance such as BER (Bit Error Rate). Due to different configurations of antennas between transmitter and receiver, there are a few issues to be solved. SVD (Singular Value Decomposition) is a common used precoding technique for beamforming, and as the design target of implementation in this thesis. This thesis proposes a reconfigurable architecture which can compute the SVD of 1 × 1~4 × 4 antenna configurations’ channel matrices. For reducing the clock delay lead of conventional memory-based architecture, this thesis employs register arrays to replace the real memory, and implements the GR-SVD algorithm by a pipelined circuit design. The design results improve not only on throughput, but also the advantages of low power and small area in chip implementation. The proposed configurable SVD processor is function-verified by the SIMIS VeriEnterprise Xilinx FPGA development board. Besides, the proposed architecture is also implemented in TSMC-90nm for demonstrating the achievement of throughput, low power and small area.
