基於IEEE P1901規格之PLC系統基頻內接收機設計; Design of Digital Baseband Inner Receiver for PLC System Based on IEEE P1901 Specification

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題名:	基於IEEE P1901規格之PLC系統基頻內接收機設計;Design of Digital Baseband Inner Receiver for PLC System Based on IEEE P1901 Specification
作者:	陳彥;Yen-Chen
貢獻者:	電機工程學系
關鍵詞:	電力線;PLC
日期:	2013-07-19
上傳時間:	2013-08-22 12:13:13 (UTC+8)
出版者:	國立中央大學
摘要:	電?線通訊 (PLC)，主要是透過電力線，將?據或資訊以?位訊號處?方法進?傳輸，因其可以直接使用既有的配電網?做為傳輸線?，?需進?額外佈線以及?接方?等使其具備最後一哩的優勢，但是因為傳輸環境的雜訊干擾以及通道衰減嚴重，使得在實際資?傳輸?方面與?想的情況會有很大的?差。因此如何解決電?線傳輸通道衰減以及抵抗雜訊干擾以提升傳輸效?，一直是各界研究的重點所在。本論文針對IEEE P1901的標準設計一基頻內接收機，由於IEEE P1901標準內所制定的前導符元為512點，而傳送的data封包為4096點，因此為了得到相對應於各子載波的通道效應，我們必須由前導符元作通道估測與內插，另外由前導符元之間的相位差我們可以由演算法得到SCO的初始值以加速SCO收斂，在硬體實現上由於前導符元與data封包各為512點與4096點，因此我們需要512點的FFT架構以及4096點的FFT架構，因此本論文實現了可變點數的memorybase-FFT，並加入dynamic scaling演算法以減少硬體面積，在頻域等化器方面採用指數型LMS演算法，相較於傳統的LMS演算法有較快的收斂速度，但是如何得到準確的指數型通道增益卻是一個問題，因此本論文針對可調整增?的?位座標軸旋轉計算器 (MGC-CORDIC)，提出改良的通道估測與等化流程，可以達到更好的效能，並且在硬體方面可與其他硬體作資源共享，進一步減少硬體面積，在模擬方面我們使用C code模擬傳輸過程及傳輸中的不理想效應，並與FPGA結果進行驗證，在最後使用90nm製程技術完成晶片設計。 Power Line Communication (PLC) is mainly about the transmission of information or data based on digital signal processing method. By directly using existing power distribution network as the transmission network, this method has the advantage of the “last mile” due to convenient connection and no need for extra wiring. However, with the noise interference in the transmission environment and the severe attenuation along the channel, there could be a huge drop off between the actual data transmission rate and the ideal data transmission rate. Therefore, the researches in all fields have been focusing on how to solve the attenuation along the power line transmission channel and to improve transmission efficiency against noise interference. In this dissertation a digital baseband receiver has been designed with respect to IEEE P1901 standard. In IEEE P1901 standard the preamble is set to be 512 points and the transmitted data packet is set to be 4096 points. Therefore, the channel interpolation must be conducted during the preamble in order to obtain the channel effect corresponding to each subcarrier. In addition, based on the phase difference between preambles the initial value of SCO can be obtained in order to accelerate the convergence of SCO. From the viewpoint of hardware realization, the FFT architectures of 512 points and 4096 points will be required according to the preamble and data packet with 512 points and 4096 points, respectively. In this dissertation the memorybase-FFT with variable points has been realized with the aid of dynamic scaling algorithm to reduce the hardware area. For the frequency domain equalizer, the exponential step size LMS algorithm has been adopted which leads to faster convergence than traditional LMS algorithm. Yet the problem is how to obtain the accurate exponential channel gain. Therefore, in this dissertation the improved channel estimation and equalization process with respect to the coordinate rotation digital computer with adjustable gain (MGC-CORDIC) have been proposed for better performance. In addition, the resource sharing mechanism with additional hardware has led to further reduction in hardware area. In order to verify the design by simulation, the C code has been used to simulate the transmission process and the undesirable effects during transmission, furthermore it has been also verified by the result of FPGA. In the end the chip design has been completed by 90 nm process technology.
顯示於類別:	[電機工程研究所] 博碩士論文

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