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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/61618


    Title: 應用於K / V 頻段低功耗混頻器之研製;Implementation on Low Power Mixers for K and V band Applications
    Authors: 郭士慶;Kuo,Shih-Ching
    Contributors: 電機工程學系
    Keywords: K頻段;V 頻段;混頻器;低功耗;K band;V band;mixer;low power
    Date: 2013-08-13
    Issue Date: 2013-10-08 15:23:50 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 本論文主要研究K / V 頻段的低功耗混頻器,共實做出三個混頻器晶片。論文主要分為兩個部分,第一部分為使用電流注入與電流再利用技術之K頻段低功耗雙平衡混頻器實做於tsmc 0.18-μm CMOS製程,利用電流再生技術達到低功耗的效果,並使用電流注入技術提高轉換增益。量測的結果顯示,當本地振盪功率為1 dBm時有最大的轉換增益0.8 dB,輸入功率1-dB壓縮點為-8 dBm,三階交互調變失真點為6 dBm,3-dB頻寬為16-30 GHz,總功率消耗為9.9 mW,電路面積為0.71 mm2。
    第二部分為使用被動結合器之閘極驅動混頻器架構,使用此架構取代吉伯特混頻器可降低供給電壓和功耗,並偏壓在弱反轉層可進一步的降低整體功耗,第二部分第一顆晶片為使用被動結合器之V頻段低功耗雙平衡閘極驅動混頻器實做於tsmc 90-nm CMOS製程,利用被動結合器將差動射頻訊號和差動本地振盪訊號相加,將相加訊號輸入電晶體閘級,利用閘極驅動的方式來混頻,且使用雙平衡架構可得到較高的隔離度,並使用逆變緩衝器提高轉換增益。量測的結果顯示,當本地振盪功率為0 dBm時有最大的轉換增益2.3 dB,輸入功率1-dB壓縮點為10 dBm,三階交互調變失真點為2 dBm,3-dB頻寬為60-66 GHz,總功率消耗為4.3 mW,電路面積為0.61 mm2。
    第二部分第二顆晶片為使用變壓結合器之K頻段次諧波低功耗單平衡閘極驅動混頻器實做於tsmc 0.18-μm CMOS製程,利用變壓結合器產生寬頻的射頻頻寬和將差動射頻訊號和差動本地振盪訊號相加,將相加訊號輸入電晶體閘級,利用閘極驅動的方式來混頻,並加入兩段四分之一波長的傳輸線來改善射頻到中頻和兩倍本地震盪到中頻的隔離度。量測的結果顯示,當本地振盪功率為1 dBm時有最大的轉換增益1 dB,輸入功率1-dB壓縮點為8 dBm,三階交互調變失真點為3 dBm,3-dB頻寬為14-30 GHz,總功率消耗為7.8 mW,電路面積為0.63 mm2。
    This thesis researches on low power mixers for K and V band applications, and achieved a total of three mixer chips. Two kinds of mixers are studied. The first one is a K band low power double-balanced mixer using current reused and current bleeding techniques that is implemented in tsmc 0.18-μm CMOS process. This design adopted current reused technique to reduce power consumption and using current bleeding technique to enhance conversion gain. The measured results show that the maximum conversion gain of -0.8 dB, an input 1-dB compression point of - 8 dBm and input third order intercept point of 6 dBm. The obtained 3-dB bandwidth is from 16-30 GHz at 1-dBm LO driving power. The total power consumption including the output buffer is 9.9 mW. The chip size is 0.63 mm2.
    Two gate-pumped mixers with passive combiners are proposed. Compared with Gilbert cell mixer, the gate-pumped mixers with passive combiners can reduce supply voltage and lower power consumption. By using weak inversion biasing can further reduce total power consumption.
    The first gate-pumped mixer is a V-band low power double balanced gate-pumped mixer using passive combiner in tsmc 90-nm CMOS process. A passive combiner is used to combine differential RF and LO signals. The combined signals are injected into each gate of the transistors of mixed stage, and utilizing gate pumped topology to yield the frequency conversion. While using double balanced toplogy to improve port-to-port isolation, and inverter buffers are adopted to increase the conversion gain. The measured results show that the maximum conversion gain of -2.3 dB, an input 1-dB compression point of -10 dBm and input third order intercept point of 2 dBm. The 3-dB bandwidth is from 60-66 GHz while the LO driving power of 0 dBm. The total power consumption including the output buffer is 4.3 mW. The chip size is 0.61 mm2.
    The second gate-pumped mixer is a K-band sub-harmonic low power single balanced gate-pumped mixer using transformer combiner in tsmc 0.18-μm CMOS process. A transformer combiner is used to produce wide bandwidth of RF frequency and combine differential RF and LO signals. The combined signals are fed into each gate of the transistors of mixed stage, and utilizing gate pumped topology to yield the frequency conversion. Two quarter wavelength transmission lines were adopted to improve the RF-to-IF and 2LO-to-IF isolations. The measured results show that the maximum conversion gain of -1 dB, an input 1-dB compression point of -8 dBm and input third order intercept point of 3 dBm. The 3-dB bandwidth is from 14-30 GHz while the LO driving power of 1 dBm. The total power consumption including the output buffer is 7.8 mW. The chip size is 0.63 mm2.
    Appears in Collections:[電機工程研究所] 博碩士論文

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