用於三維積體電路之測試整合與良率提升技術; Test Integration and Yield-Enhancement Techniques for 3-D ICs

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/61662

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题名:	用於三維積體電路之測試整合與良率提升技術;Test Integration and Yield-Enhancement Techniques for 3-D ICs
作者:	周哲緯;Chou,Che-Wei
贡献者:	電機工程學系
关键词:	三維積體電路;測試;良率;3-D IC;Test;Yield
日期:	2013-08-27
上传时间:	2013-10-08 15:25:02 (UTC+8)
出版者:	國立中央大學
摘要:	使用穿矽穿孔(through-Silicon-via，TSV)來垂直連接多層二維晶粒(Die）的三維技術是近來新興的積體電路設計技術之一。三維積體電路相較於現今的二維單晶片系統(system-on-chip，SOC)有許多的優點，如大幅縮短全域導線的長度、增進電路的效能與異質整合等等好處。然而，此三維積體電路設計技術目前仍然存在著許多挑戰，包含設計、製造、測試、良率、可靠度等。在三維積體電路要量產之前，這些挑戰都需要被克服。其中，三維積體電路的測試與良率是其中相當關鍵的問題與挑戰。因此，對三維積體電路而言，有效的測試與良率提升技術是非常重要的。一個三維晶片通常是由多個被穿矽孔垂直連接的二維晶粒所組成的，由於這些二維晶粒可能來自於不同的來源，所以一個用來統合控管這三維晶片中的可測試性設計(design-for-test，DFT)的標準化測試控制介面是非常必須的。在論文的第一部分，我們針對邏輯跟記憶體晶粒提出了標準化的測試介面，並且這些介面可以用階層式的控制方法將其整合在一起。所提出之測試介面可以用在黏合前測試、黏合中測試、黏合後測試和最後測試階段，且這些測試介面最少僅需要四個測試腳位。再者，我們所提出的測試介面在執行電路板層級測試時是完全與IEEE 1149.1測試標準相容的。實驗結果顯示，我們所提出的階層式測試控制整合介面的面積在用於ITC’99的b19電路與TSMC 0.18μm的製程下，只有0.24％的額外面積消耗。此外，我們所提出之測試整合方法亦已實現在一個三維測試晶片上並驗證。在論文的第二部分，我們針對JEDEC的寬輸入輸出動態隨機存取記憶體(wide I/O DRAM）提出了一高度可程式化的內建自我測試電路。寬輸入輸出動態隨機存取記憶體與一般動態隨機存取記憶體主要的差異在於最小的突發長度(burst length），寬輸入輸出動態隨機存取記憶體與一般動態隨機存取記憶體所能執行的最小突發長度分別是二和一，這使得使用現存的March測試演算法來測試寬輸入輸出動態隨機存取記憶體並不能達到100％的耦合錯誤(coupling faults）的錯誤覆蓋率(fault coverage），為此，我們提出了一個測試演算法來使得寬輸入輸出動態隨機存取記憶體的耦合錯誤的錯誤覆蓋率達到100％。此外，我們也提出了一重複利用測試腳位的方法來重複利用寬輸入輸出動態隨機存取記憶體已有的邊界掃描鍊的測試腳位來控制所提出之內建自我測試電路，所以使得有內建自我測試電路的DRAM晶粒的腳位數與無內建自我測試電路的DRAM晶粒的腳位數完全相同。最後，所提出的內建自我測試電路可以支援多種的March測試演算法與多種的記憶體配置組合。實驗結果顯示出了所提出之內建自我測試電路的面積消耗是相當小的，舉例來說，當應用在32-Gbit的寬輸入輸出動態隨機存取記憶體與使用TSMC 90nm的製程時，我們的內建自我測試電路僅僅只有0.32％的面積消耗。在論文的第三部分，我們針對三維記憶體提出一完整的良率提升技術，其中包含了提出一晶粒間備份元件的架構來提升三維記憶體的良率；並針對使用不同的黏合技術且擁有晶粒間備份元件的三維記憶體提出了三種堆疊的流程；最後針對三維記憶體的修復議題提出了一內建自我修復電路的架構，其中的內建備份元件分析模組可以有效地分析並分配晶粒間的備份元件。模擬結果顯示出我們所提出之良率提升技術可以有效地增進三維記憶體的良率。我們模擬了10片晶圓(wafer），每片晶圓上有4350個記憶體晶粒，每個記憶體晶粒的容量是512K bytes，且每個記憶體晶粒有兩個記憶體區塊。每個記憶體區塊有256K bytes且每個記憶體區塊各有兩個備份列元件與兩個晶粒間備份行元件。並假設錯誤分布為60％的單一位元錯誤(single cell fault）、20％的錯誤列(faulty row）與20％的錯誤行(faulty column）分布下，當採用晶粒對晶粒(die-to-die）、晶粒對晶圓(die-to-wafer）與晶圓對晶圓(wafer-to-wafer）的黏合技術時，使用我們提出的良率提升技術分別可以得到9.588％、9.584％與14.462％的三維記憶體良率的改進。應用在2M-bit的記憶體晶粒時，提出之內建自我修復電路面積消耗約1.77％，所以提出之內建自我修復電路面積消耗是相當小的 Three-dimensional (3-D) integration technology using through-silicon via (TSV) is one emerging integrated circuit (IC) technology. The 3-D integration technology offers many advantages over the 2-D integration technology, such as power reduction, performance improvement, heterogeneous integration, etc. However, many challenges should be overcome before the volume production of 3-D ICs become possible. Among these challenges, test and yield are two key challenges. Effective test and yield-enhancement techniques thus are important for 3-D ICs. A 3-D IC consists of multiple dies connected vertically by TSVs. Since the dies may come from different sources, a standardized test control interface for integrating the designfor-testability (DFT) circuits in each die thus is imperative. In the first part of this thesis, we propose test interfaces for the logic and memory dies, and these test interfaces can be integrated in a hierarchical method. The test interfaces can support the prebond, midbond, postbond, and final tests. The minimum number of required test pads of the proposed test interfaces is only four. Furthermore, the test interfaces are compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces is very small, which is about 0.24% for the ITC’99 b19 benchmark using TSMC 0.18μm CMOS technology. A 3-D test chip is also implemented to emonstrate the proposed test integration methodology. In the second part of this thesis, we propose a programmable built-in self-test (BIST) scheme for JEDEC wide I/O DRAMs. One main difference between a wide I/O DRAM and a general DRAM is the minimum burst length. The minimum burst length of a wide I/O DRAM and a general DRAM is 2 and 1, respectively. That causes that using existing March test algorithms to test wide I/O DRAM cannot achieve 100% fault coverage for coupling faults. A test algorithm thus is proposed to achieve 100% fault coverage of coupling faults as well. Furthermore, a test pin reusing methodology is proposed to reuse the test pins of boundary scan of the wide I/O DRAM to control the BIST circuit. Thus, the number of pins of the DRAM die with BIST is the same as that of the DRAM die without BIST. inally, the programmability of the proposed BIST can support various March test algorithms and various memory configurations. Experimental results show that the area cost of the BIST is very small, which is about 0.32% for 32G-bit DRAM using TSMC 90nm CMOS technology. In the third part of this thesis, we present yield-enhancement techniques for 3-D RAMs. An inter-die redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with inter-die redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is also proposed to perform the 3-D RAM repair. Its built-in redundancy analysis (BIRA) module can allocate the inter-die redundancies efficiently. Simulation results show that the proposed yield-enhancement techniques can drastically improve the final yield of 3-D RAMs. We simulated 10 wafers and each wafer has 4350 RAM dies. The size of a RAM die is 512K bytes, and each RAM die has two blocks. The size of a block is 256K bytes and each block has two spare rows and two inter-die spare columns. Also, the fault distribution of the simulated RAM dies with 60% single-cell faults, 20% faulty rows, and 20% faulty columns is assumed. The yield improvement of 3-D RAMs with proposed yield-enhancement techniques is 9.588%, 9.584%, and 14.462% by using die-to-die, die-to-wafer, and wafer-to-wafer bonding techniques. And the area overhead of the proposed BISR scheme in a RAM die is small, which is about 1.77% for a 2M-bit RAM die.
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