具全自動自我校正技術之 內建抖動量測電路應用於高速串列傳輸; A Built-In Jitter Measurement Circuit with Auto-Calibration Techniques for High Speed Serial Link

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題名:	具全自動自我校正技術之內建抖動量測電路應用於高速串列傳輸;A Built-In Jitter Measurement Circuit with Auto-Calibration Techniques for High Speed Serial Link
作者:	鄭士平;Cheng,Chih-ping
貢獻者:	電機工程學系
關鍵詞:	全自動自我校正;內建抖動量測;時間放大器;多相位振盪器;Auto-Calibration;Built-In Jitter Measurement;Timing Amplifier;Multi-phase Oscillator
日期:	2013-10-08
上傳時間:	2013-11-27 11:33:31 (UTC+8)
出版者:	國立中央大學
摘要:	電路密度和電路操作頻率隨著製程演進而逐漸提升，導致抖動量測的成本提高。為了降低抖動量測的成本，有人提出了內建測抖動量測電路。然而，內建抖動量測電路容易受到製程變異的影響，使抖動量測的解析度發生漂移。為了降低解析度的漂移量，需要對抖動量測電路進行校正，但傳統的校正方式的時間效率不高。因此，本論文提出可應用於高速串列傳輸且具全自動自我校正技術之內建抖動量測電路。為了量測週期對週期抖動，我們採用了無需額外參考信號源的自我取樣電路，而為了能改善解析度，此次電路採用了多相位振盪器和時間放大電路。多相位振盪器被用來產生高頻的多相位取樣頻率，提供多項位取樣電路使用，而時間放大電路則用來放大輸入時間差，強化整體解析度。為了降低製程變異的影響，自動校正電路對多相位振盪器的解析度以及時間放大電路的增益進行校正。經過自動校正電路改善後，整體解析度的漂移量降低了65%。此次內建抖動量測晶片使用TSMC 180 nm 1P6M CMOS製程實現，其量測3 GHz 時脈抖動之解析度為2.58 ps，整體晶片面積為908 um × 908 um，而核心電路面積為476 um × 372 um，供應電壓為1.8 V，電路功率消耗為58 mW。雖然功率消耗有些高，但內建抖動量測電路只在抖動量測時才啟動。 With the circuit density and operational frequency increasing, the cost of off-chip jitter measurement rises. Built-in jitter measurement (BIJM) circuits are invented to reduce the off-chip jitter measurement complexity and therefore, the cost is reduced. However, the BIJM resolution is sensitive to process variation, and the conventional calibration method lacks time efficiency. Thus, this thesis presents a BIJM circuit with auto-calibration techniques for 3 GHz serial link clock signal measurement. To measure the cycle-to-cycle jitter, a self-referenced circuit, without an external reference clock, is applied. A multi-phase oscillator (MPO) and a timing amplifier (TA) are used to generate the high-speed multi-phase outputs for a multi-phase sampler (MPS) and to enhance the timing resolution. In order to decrease the process variation impact, the calibration circuits are applied to calibrate the MPO timing resolution and the TA gain. They are rewarded with a reduction of the variation of the total timing resolution by 65%. The jitter measurement resolution of 3 GHz clock is 2.58 ps after calibration. The experimental chip of the proposed BIJM was implemented by TSMC 180 nm 1P6M CMOS process. The chip size is 908 um × 908 um. The core area is 476 um × 372 um. The power consumption is 58 mW including calibration circuit and the supply voltage is 1.8 V. Although the power consumption seems to be high, the proposed BIJM circuit is active only when jitter measurement is required
顯示於類別:	[電機工程研究所] 博碩士論文

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