| 摘要: | 提升射頻功率放大器之效率將可改善行動產品的散熱問題以及增長產品的使用時間。可調式負載技巧可用於提升功率放大器在輸出功率退回時的效率。我們設計了一1.95 GHz的功率放大器，並使用鐵電可變電容於其輸出匹配網路中，以提供可調之負載阻抗，展示功率放大器效率之提升。
我們發展一鐵電薄膜平行板電容之製程。量測結果顯示，面積為10×10 μm2之鐵電可變電容其電容值可達2 pF。當偏壓約7 V時，鐵電可變電容容值可以變化至0 V時電容值的一半；於1.95 GHz，電容之Q值皆大於20。
我們使用離散式的pHEMT電晶體，設計一操作於1.95 GHz的可調式功率放大器。電晶體汲極偏壓為5 V，閘極偏壓為0.45 V，此時靜態電流為256 mA，放大器操作於Class AB區域。我們使用ADS，在不同輸入功率下進行負載牽引模擬；接著使用Matlab找出在不同輸出功率下可達最佳PAE之負載阻抗值。基於這些最佳負載阻抗值，我們進一步設計一鐵電基可調式匹配網路；其阻抗變化範圍須涵蓋所需之最佳負載阻抗。
我們使用自行發展的製程於一藍寶石基板上製作了鐵電基可調式匹配網路。在同一基板上，我們使用銀膠來安置電晶體及其他被動元件，以完成功率放大器之製作。量測結果顯示，可調式匹配網路之阻抗變化範圍與模擬結果相近。於1.95 GHz下，可調式功率放大器之最大輸出P1dB約為13.1 dBm，小訊號增益約為6 dB。調整可調式匹配網路的偏壓可使功率放大器在3 dB功率退回範圍內皆達到效率之提升及功耗之改善。在3 dB功率退回時，直流功耗可從約660 mW降低至 570 mW。
本論文發展了一鐵電可變電容之製程，並將鐵電可變電容應用於可調式匹配網路。最後，藉由調整可調式匹配網路的偏壓，我們驗證功率放大器於功率退回區域之效率確可得到改善。?
By enhancing the power efficiency of RF power amplifiers (PAs), the heating problem of mobile devices can be alleviated and their talk time can be extended. Variable load technique has been proposed to enhance the efficiency of PAs at power back-off. In this work, a PA is designed at 1.95 GHz. Ferroelectric capacitors are used in the output matching network of the PA to provide a tunable load impedance, demonstrating efficiency enhancement.
A fabrication process for ferroelectric parallel-plate capacitors is developed. Measurement results show that, the capacitance of a ferroelectric varactor with an area of 10×10 μm2 is 2 pF. When biased at about 7 V, the capacitance of the ferroelectric varactor can be reduced to half of the capacitance at 0-V bias. At 1.95 GHz, the quality factor of the ferroelectric varactor is above 20.
A 1.95-GHz tunable PA is designed using a commercially available discrete pHEMT transistor. The drain and gate of the transistor are biased at 5 V and 0.45 V, respectively, with the quiescent current being 256 mA. The power amplifier operates in Class AB region. Load-pull simulations under different input power levels are performed using ADS. The simulated data is then processed using Matlab to find the optimum load impendences that maximize the power-added efficiency (PAE) at various output power levels. After that, we then proceed to design a ferroelectric-based tunable matching network, of which the impedance coverage must encompass the desired optimum load impendences.
Based on the fabrication process developed by us, the ferroelectric-based tunable matching network is on a sapphire substrate. On the same substrate, the pHEMT transistor and other passive components are mounted using epoxy, completing the fabrication of the tunable PA. On wafer measurement is performed. The measured impendence coverage of the tunable matching network is found to be close to the simulated impedance coverage. At 1.95 GHz, the maximum output P1dB of the tunable PA is approximately 13.1 dBm. Its small-signal gain is about 6 dB. By adjusting the bias voltages of the tunable matching network, the efficiency enhancement and the dc power consumption reduction are observed as long as the power back-off is within 3 dB. At 3-dB back-off, the dc power consumption is reduced from 660 mW to 570 mW.
In this work, a fabrication process for ferroelectric varactors is developed. A tunable matching network is designed based on the ferroelectric varactors. Finally, by changing the bias voltages of the tunable matching network, it is demonstrated that the efficiency of the PA at power back-off is indeed enhanced. |
