隨著積體電路的快速發展，人們對於電路的要求逐漸提升，然而印刷電路板為了符合設計者的需求，繞線儼然已成為一個至關重要的議題。為了電路的信號穩定性與完整性，繞線處理的規格傾向於使用平行匯流排的觀念，要求等長、等距且盡可能地緊密匯合在一起。 在眾多的印刷電路板繞線文獻當中，大部分都在區域繞線 (Area Routing) 階段作線長匹配的處理，鮮少有研究提早於逃脫繞線 (Escape Routing) 階段作此考量。我們提出了於逃脫繞線階段考量線長匹配問題的演算法，並且以平行匯流排的規格讓信號得以更優質的方式傳輸；此外，由於提早處理線長匹配問題，能有效地利用逃脫繞線階段的繞線資源，在區域繞線階段也可省去大量的面積，這將不同於一般的線長匹配考量僅為了滿足系統的時序設計而使用大量的蛇形走線 (Snaking)。 實驗結果顯示，我們所提出的方法可以在極短的時間內達到百分之百的線長匹配，也可省去大量的區域繞線面積。 As the integrated circuit advances, the circuit requirements by designers increase. In order to meet the needs of designers, the printed circuit board routing seems to be a critical issue. For signal stability and integrity of the routing, the concept of the parallel bus－including requirement of equal length, equidistance of nets and routing closely as possible－ is tend to be used as the specification of circuits. Among previous works for the printed circuit board routing, a majority of them considered length-matching issue in area routing stage. Hence, we proposed an algorithm which considers length-matching issue in an early stage, escape routing stage. With the use of the specification of a parallel bus, the routing allows better signal transmission. Furthermore, since we consider length-matching issue in advance, we can use the routing resources effectively in escape routing stage. Also, a lot of additional routing area can be avoided in area routing, and it decreases snaking routing significantly. As experimental results showed, our algorithm can save a lot of area in area routing, and achieve one-hundred-percent length matching within very short runtime.
