本論文以降低傳統Systolic Sorted QR分解的運算成本為研究目標。我們深入的研究了QR分解在Systolic架構下造成的CORDIC閒置問題以及傳統模擬不夠仔細下造成的Word-Length遷就問題。我們提出了CORDIC Reusing設計以利大幅的縮減硬體面積並增加CORDIC使用率，藉由仔細的硬體模擬而排除了不必要的Word-Length遷就，再搭配刪除不必要之排序級數來縮減排序電路。本論文以4x4 MIMO系統的需求設計了高速且低複雜度的Modified Systolic Sorted QR分解電路，相較於傳統之Systolic Sorted QR分解，本論文所呈現的硬體總縮減量高達33.8%。最後使用TSMC-90 nm製程來實現所設計之電路，以驗證所提出之電路設計措施的有效性。; The research objective of this treatise is to reduce the computational cost of traditional systolic sorted QR decomposition. We had studied two kinds of issue in traditional systolic sorted QR decomposition. One is the CORDIC Idling which is caused by systolic architecture and the other is the Word-Length Compromising resulted from the un-careful simulation. We propose the CORDIC Reusing method which can reduce circuit area effectively and increase CORDIC utilization,carefullyconductsimulation to achieve no unnecessary word-length compromising, andcoordinate the Sort Reduction method to reduce the complexity of sorting circuit without BER performance loss. In this treatise, we present a high-speed and low complexitymodifiedsystolic sorted QR decomposition for 4 × 4 MIMO detector. Comparing with traditional systolic sorted QR decomposition, our circuit has an enormous reduction of 33.8%. In the end, we use TSMC-90 nm to implement our design.
