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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/63543


    Title: 應用於生醫訊號具RC時間常數校正機制之低功率連續時間三角積分類比數位轉換器;A Low-Power Continuous-Time Delta-Sigma ADC with RC Time-Constant Calibration Technique for Biomedical Signals Application
    Authors: 黃昶暘;Huang,Chang-Yang
    Contributors: 電機工程學系
    Keywords: 連續時間;離散時間;三角積分調變器;數位降頻濾波器;反交疊濾波器;雜訊轉移函數;訊號轉移函數;交換式電容電路;Continuous-Time (CT);Discrete-Time (DT);Delta-Sigma Modulator (DSM);Digital Decimation Filter;Anti-Aliasing Filter (AAF);Noise Transfer Function (NTF);Signal Transfer Function (STF);Switched-Capacitor Circuit (SC);Biquad Filter
    Date: 2014-01-20
    Issue Date: 2014-04-02 15:48:19 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 隨著醫學與超大型積體電路的快速成長,如今的生理訊號量測儀器已朝向可攜式發展,低功率的訴求在生醫應用中也日益重要。如何降低功耗與面積以滿足生醫儀器的可攜式和電池長效性已成為生醫應用的重要課題。
    在生醫系統中,一個高解析度、低功耗的類比數位轉換器是重要的組成元件之一。藉由三角積分調變器 (DSM) 超取樣的特性,可有效降低前端類比濾波器設計的複雜度,進而減少整體晶片面積。然而一般的DSM大多是由交換式電容電路實現,為離散時間 (DT) 的系統。其開關快速切換的行為則需要更快的硬體來支援,這將造成大量的功率消耗,因此本論文選用連續時間 (CT) 的三角積分調變器以減緩硬體需求。此外,CT DSM本身具有反交疊濾波的特性,可進一步降低前端類比濾波器的複雜度。然而,CT DSM存在與溫度、製程變異嚴重相依的缺點,故本論文提出RC時間常數的校正方法,以自動補償RC時間常數的變異。此校正方法同時也能校正取樣頻率造成的係數偏差,因此即使取樣頻率發生變化,調變器中的迴路濾波器仍能正常運作。
    本論文設計之CT DSM電路在10 kHz頻寬、128倍超取樣率、±0.5 V的輸入振幅以及1.8 V的供應電壓下,模擬可達到的訊號雜訊失真比 (SNDR) 為82.62 dB,有效位元 (ENOB) 為13.43位元,功率消耗約為76.98 μW (調變器+RC時間常數校正電路)。使用台積電TSMC 0.18μm CMOS 1P6M製程實現,其整體晶片面積約為1.408mX1.558m。; With the rapid development of the medical science and VLSI technology, the bio-signal measurement systems have been developed towards portability. Therefore, the low-power demands in biomedical application are increasingly important as well. How to reduce the power consumption and area for satisfying the portability as well as the long battery life-time requirements of biomedical instruments have become the important issues.
    A high-resolution and low-power analog-to-digital converter is also one of the critical components that comprise the biomedical system. By taking the advantage of oversampling technique in delta-sigma modulators, the design complexity of analog anti-aliasing filter can be relaxed, and then resulting in reducing the overall chip area. However, the general DSMs consist of switched-capacitor (SC) circuit, so as a discrete-time system. The fast switching behavior of the switches requires a high-speed hardware to support, thus causing more power consumption. In this thesis, we choose the continuous-time delta-sigma modulators (CT-DSM) to ease the requirements of hardware. Furthermore, there is an inherent characteristic of implicit anti-aliasing filter in CT DSM; the design complexity of anti-aliasing filter can be further reduced as well. However, the drawback of a CT DSM is the dependence on the environment temperature and process variation. Therefore, the RC time-constant calibration method is proposed for automatically compensating the variations of RC time-constant. The method also can calibrate the coefficient errors introduced by the variation of sampling frequency. Even if the sampling frequency is changed, the function of loop filter in CT DSM still works very well.
    The modulator achieves 82.62dB SNDR, 13.43bit ENOB, and power consumption 76.98μW at 10kHz signal bandwidth with X128 OSR, 1Vp-p amplitude, and 1.8V power supply. It's fabricated in the TSMC 0.18μm 1P6M CMOS process, and chip area is 1.408mX1.558m.
    Appears in Collections:[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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