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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/64564

    Title: 基於全通網路之類比式及數位式相位偏移器;Analog and Digital Phase Shifters Based on All-Pass Networks
    Authors: 李曉昀;Li,Hsiao-Yun
    Contributors: 電機工程學系
    Keywords: 相位偏移器;全通網路;鐵電可變電容;寬頻;相位誤差;Phase Shifter;All-Pass Network;Ferroelectric Capacitor;Band-Width;Phase Error
    Date: 2014-06-26
    Issue Date: 2014-08-11 18:42:07 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 本論文使用全通網路的架構設計類比式與數位式相位偏移器。我們利用增加電路階數可提升頻寬的概念來解決單級全通相位偏移器頻寬較窄的問題。本論文包含兩個電路,分別為:利用鐵電可變電容實現之類比式全通相位偏移器及使用TSMC 0.18-µm CMOS 製程實現之六位元寬頻全通相位偏移器。
    基於本實驗室發展之鐵電薄膜可變電容製程,我們設計並製作一類比式全通相位偏移器。量測結果顯示,當鐵電可變電容偏壓至10 V時,單級全通網路的相位偏移量可達85°以上。而在相位偏移量最大的頻率之植入損耗小於2 dB及返回損耗大於12 dB。我們使用MATLAB模擬軟體,將單級全通相位偏移器之S參數量測結果,串接為四級全通相位偏移器之模擬結果,其相位偏移量最大值可達180°,且從2.1 GHz到3.25 GHz之相位誤差皆小於±3°,頻寬為43%。
    另外,論文中分析了單級與兩級使用內接切換式電容之全通網路,並利用分析之結果設計一全差動式六位元相位偏移器。其中,180°的相位偏移器使用SPDT開關實現,而 90°及45°的相位偏移器是使用兩級全通網路內接切換式電容的架構實現。最後三個位元是使用單級全通類比式相位偏移器所實現,其中包含三位元的數位式可變電阻,用來等效三位元數位式相位偏移器。量測結果顯示,從2.19 GHz到2.82 GHz,均方根相位誤差均小於2°,相對應的頻寬為25%。在頻寬範圍內,返回損耗均大於9.2 dB,振幅誤差在±1 dB之內。在2.4 GHz時,其平均植入損耗為14.6 dB。
    ;In this thesis, analog and digital phase shifters are designed based on all-pass networks. Cascading multiple stages of all-pass networks is adopted as a remedy for their narrow phase-shift bandwidth. Two wideband and low-phase-error phase shifters are covered in this work: analog phase shifter using ferroelectric varactors and digital phase shifter with 6-bit resolution in TSMC 0.18-µm CMOS process. Both of them are designed based on all-pass networks.
    Based on the ferroelectric thin-film varactor process developed at National Central University, we design and fabricate analog all-pass phase shifters. Measurement results show that maximum phase shift of more than 85° is achieved with a single-stage ferroelectric-based all-pass phase shifter when biased at 10 V. At the frequency where maximum phase shift occurs, the insertion loss is less than 2 dB and the return loss is greater than 12 dB. Based on the measured scattering parameters of single-stage all-pass phase shifter, a four-stage all-pass phase shifter is simulated. Simulation results show that maximum phase shift of 180° can be achieved whereas the phase error is within ±3° between 2.1 GHz and 3.25 GHz, which translates to 43% bandwidth.
    Besides, in this thesis, single-stage and two-stage all-pass networks with internal switched capacitors are analyzed. Based on the analysis, a fully-differential digital phase shifter with 6-bit resolution is designed. The 180° phase-shifting bit in the phase shifter is realized using a pair of SPDT switches. The 90° and 45° bits are designed using the two-stage all-pass phase shifter analyzed in this work. The three least significant bits are implemented using an analog single-stage all-pass phase shifter along with a 3-bit digital potentiometer. Measurement results show that the rms phase error is less than 2° from 2.19 GHz to 2.82 GHz, corresponding to a bandwidth of 25%. Within the frequency range, the return losses are greater than 9.2 dB and the amplitude error is within ±1 dB. At 2.4 GHz, the average insertion loss is 14.6 dB.
    In conclusion, we successfully demonstrate the potential of using all-pass networks for designing wideband and low-phase-error analog and digital phase shifters.
    Appears in Collections:[電機工程研究所] 博碩士論文

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