應用於5-GHz CMOS射頻前端電路之低電壓自偏壓式混頻器與高線性化功率放大器之研製;The Implementation on Low Voltage Self-Bias Mixer and High-Linearity Power Amplifier for 5-GHz Band CMOS RF Front-End

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题名:	應用於5-GHz CMOS射頻前端電路之低電壓自偏壓式混頻器與高線性化功率放大器之研製;The Implementation on Low Voltage Self-Bias Mixer and High-Linearity Power Amplifier for 5-GHz Band CMOS RF Front-End
作者:	林貴城;Lin,Kuei-cheng
贡献者:	電機工程學系
关键词:	雙平衡式混波器;折疊架構;自偏壓式技術;整合被動元件;功率放大器;後失真線性化技術;Gilbert cell mixer;folded-switch topology;self-bias current reuse technique;integrated passive devices;power amplifier;post-distortion
日期:	2014-07-16
上传时间:	2014-10-15 17:08:49 (UTC+8)
出版者:	國立中央大學
摘要:	因為互補式金氧半導體(CMOS)製程技術的進步，滿足了低功耗與高整合度的需求，適用於多頻帶射頻（RF）收發器設計。CMOS射頻收發器已被廣泛應用於消費性產品和無線通訊系統。現今，節能設計機制在CMOS射頻收發器的設計需求變得非常重要，相關研究議題如下：第一、射頻收發器各子電路為了實現低功耗和低電壓的設計需求，其電路將會面臨架構創新的重要問題。隨著低耗電、低電壓需求，傳統的雙平衡式混波器(double-balanced mixer)電路為堆疊架構，將無法正常操作，必須選擇其他電路架構以滿足低電壓操作，例如折疊架構。第二、CMOS製程所提供被動元件損耗較大，將會增加功耗來維持電路效能。整合被動元件(integrated passive device: IPD)製程採用玻璃基板，適合用來實現低損耗被動元件，透過覆晶轉接(Flip-chip)來與CMOS主動元件整合，成為系統封裝SiP來實現高效能特性。第三、功率放大器大多操作在高輸出功率範圍，來驅動無線通訊發射器的天線。功率放大器操作在此範圍通常是非線性的，在輸出節點處會產生嚴重失真。通常，在線性功率控制上，採功率直接調降(power back-off)的方式以滿足線性度要求，基本上會降低功率增加效率(power added efficiency: PAE)。為了改善此現象，使用線性化技術以滿足線性度和PAE的要求。本篇論文主要聚焦在應用於5 GHz射頻電路之低電壓自偏壓式混頻器與高線性化功率放大器之設計與研製。在混波器方面，電路設計概念主要以低電壓操作之應用，並以高轉換增益(conversion gain)、良好線性度與較佳隔離度等方向作為設計目標。在功率放大器方面，電路設計概念主要使用後失真線性化技術(post-distortion)以提升線性輸出功率、效率與低誤差向量幅度等方向作為設計目標。第二章提出一顆低電壓、低功率消耗操作之自偏壓式技術應用於交流耦合折疊開闢式混頻器(AC-couple folded switch mixer)並以台積電(Taiwan Semiconductor Manufacturing Company, tsmcTM)90奈米CMOS製程研製而成。在低供應電壓操作下，此混波器可以獲得良好的輸入三階截斷點(input third-intercept point: IIP3)及轉換增益。在供應電壓為0.7 V時，整體電路之最佳性能指數(Figure of Merit : FOM)經由計算可達到15.5。將此混波器與差動對低雜訊放大器、多相濾波器(poly-phase filter)組成一5-6 GHz射頻前端直接降頻接收器，在供應電壓為1 V操作下，實際量測後可獲得26 dB之轉換增益與2.7 dB之雜訊指數。隔離度與輸入三階截斷點分別為50 dB與-12 dBm。第三章是介紹使用一整合被動元件(IPD)的薄膜製程來降低放大器的雜訊指數，目標為降低射頻前端接收機裡第一級低雜訊放大器的雜訊指數，以改善接收機靈敏度。利用覆晶(flip-chip)的封裝技術垂直整合了CMOS 0.18 m與IPD兩種製程技術，實現了一個CMOS與IPD製程之低雜訊放大器設計，相較於使用全積體化的低雜訊放大器，雜訊指數可以改善0.6 dB，整體電路之最佳性能指數可達到16.72。第四章實現一阻抗轉換比為1:4 IPD figure 8 功率結合變壓器應用於CMOS之功率放大器，功率結合變壓器設計採用IPD製程來設計，達到高功率輸出特性。在放大器的偏壓電路選擇可適性偏壓，可達到增益延伸與提升線性度，且不會產生額外的功率消耗。此放大器可達飽和輸出功率28 dBm、最大功率增進效率(PAE)為25 %。相較於使用全積體化的CMOS變壓器相比，可提升輸出功率1.3 dB、PAE為6 %。第五章提出一個使用後失真線性化技術的功率放大器，當開啟後失真線性化技術時，可以在1 dB壓縮點改善輸出功率，其1 dB壓縮點輸出功率與飽和輸出功率僅差0.2 dB。與未開啟後失真線性化技術時做比較，其放大器可以改善線性輸出功率2.3 dB。另外，在功率放大器裡的射頻扼流圈(RF choke)採用晶片級bondwire螺旋電感。在5GHz頻率，此電感的品質因數是32，比晶片型螺旋電感的品質因數高出3倍。應用於此線性化功率放大器可以分別改善1.6 dB輸出功率以及7.3 % PAE，最後在第六章做一個總結。 ;Since the advantage of CMOS technology satisfies the requirements of the low power consumption and high integration level in multi-GHz radio frequency (RF) transceiver designs, RF CMOS transceiver has been popularly applied in consumer products and wireless communications. Nowadays, the demand of green-power design mechanism in CMOS RF transceiver design becomes important, and the related research topics are listed as following. First, the design goals for low-power and low-voltage performances are always the critical issue to innovate for RF transceiver blocks. Conventional Gilbert cell mixer with three- cascode stages is difficult to keep all transistors operating in saturation region under low-voltage. The low-voltage operation requires modified circuit architecture, such as the folded-switch topology has been proposed to reduce the supply voltage and power consumption. Second, the passive device in CMOS process has high insertion loss which increases the power consumption to maintain circuit performance. The integrated passive devices (IPD) technology with glass substrate reduces the loss of substrate to improve the efficiency of RF circuits. The CMOS and IPD chips are assembled by flip-chip technology, which achieves high efficiency RF system-in-a-package (RF-SiP) wireless product. Finally, power amplifier (PA) is used to provide high output power to drive the antenna of a transmitter in wireless communications. PA usually operates in high non-linearity region which produces serious distortion at the output node. In practice, PA is operated at power back-off mode to meet the linearity requirement that substantially degrades power added efficiency (PAE). The linearization technique is required to meet the linearity and PAE specifications. This thesis primarily targets at the design and implementation of low voltage self-bias mixer and high-linearity PA for 5 GHz band CMOS RF front-end. The design goals of the mixer are low voltage operation, high conversion gain (CG), high linearity, and high port-to-port isolations. The PA design uses a post-distortion linearizing technique to achieve high linear output power, high PAE and low error vector magnitude (EVM). In the thesis, Chapter 2 proposes an AC-coupling folded-switch double balanced mixer (DBM) that uses a novel low-voltage, low power self-bias current reuse technique in taiwan semiconductor manufacturing company (tsmcTM) standard 90 nm CMOS technology. At low supply voltage operation, the proposed DBM obtains good third-order intermodulation intercept point (IIP3) and CG at 5 GHz band. At the supply voltage of 0.7 V, the mixer achieves the best figure of merit (FOM) of 15.5 at 5 GHz band. Two designed mixers are combined with a differential low noise amplifier (DLNA), a poly-phase filter, and two buffer amplifiers to form a 5-6 GHz direct-conversion receiver (DCR) architecture. The DCR achieves a CG of 26 dB with a noise figure (NF) of 2.7 dB from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP3 of the DCR is -12 dBm. The first stage of a DCR is typically low noise amplifier (LNA) and requests a minimum NF to improve the sensitivity of the receiving chain. Chapter 3 adopts a thin-film process of integrated passive device (IPD) technology which improves the NF of LNA. Our design combines standard 0.18 m CMOS process, IPD and flip-chip package technologies with a vertical heterogeneous integration to achieve a CMOS-IPD LNA. This fully integrated LNA improves an NF of 0.6 dB as compared to as compared to its counterpart without IPD. The CMOS-IPD LNA achieves the FOM of 16.72 at 5.2 GHz band. Chapter 4 presents a CMOS-IPD PA which uses an impedance transformation ratio of 1:4. The 1:4 figure 8 power-combining transformer was also fabricated using IPD process to achieve high output power level. The PA uses an adaptive bias linearizer that extends the power gain and improves the linearity without extra power. This PA provides a saturation output power of 28 dBm and a PAE of 25 %. The CMOS-IPD PA improves the output power and PAE of 1.3 dB and 6 %, respectively, as compared to its counterpart without IPD. Chapter 5 presents a 5 GHz CMOS PA using post-distortion linearizing technique. When the linearizer is turned on, the proposed PA improves the output power at 1 dB gain compression point (OP1dB). Only 0.2 dB discrepancy between the output P1dB and saturated output power is observed. The output P1dB of the PA with post-distortion linearizier is improved by 2.8 dB as compared to its counterpart without linearizer. Furthermore, the RF choke in the PA uses a wafer-level bondwire spiral inductor (BSL). The BSL achieves a Q of 32 which is three times higher than that of a conventional CMOS standard spiral inductor at 5 GHz. The output power and PAE of the PA with wafer-level BSL are improved by 1.6 dB and 7.3 % as compared to those of the fully integrated CMOS PA. Finally, Chapter 6 draws a brief conclusion.
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