隨著超大型積體電路的快速演進，電路繞線的問題也愈趨龐大。為解決日漸複雜的繞線問題，傳統上常習慣將繞線分為兩大階段進行處理，分別為全域繞線階段（Global Routing Stage）與細部繞線階段（Detailed Routing Stage）。 現今已經有相當大量的全域繞線相關文獻，但其中絕大部分皆沒有考慮細部繞線階段可能產生的壅塞問題，這將導致即使完成了全域繞線，仍有相當大的機率無法得到無壅塞（Congestion-Free）的細部繞線結果。因此，本篇提出了適用於全域繞線階段的局部壅塞模型（Local Congestion Model），將局部壅塞的資訊帶入全域繞線進行考量；並且調整了傳統全域繞線的演算法流程，使其更能夠應對考量局部壅塞時產生的額外溢出。加入此一局部壅塞模型的全域繞線器將能夠提早預知局部壅塞的情形，並且提早迴避壅塞區域（Congested Region），或者識別不可繞（Unroutable）的電路。 實驗結果顯示，本篇所提出的方法可以在短時間內建立局部壅塞模型，藉此可於全域繞線階段提早得知細部繞線階段的壅塞情形。 ;As the integrated circuit advances, the problem size of ASIC routing grows fast. To solve such complex problem of routing, it is traditionally separated into global routing stage and detailed routing stage. There is a large amount of global routing works, but most of them did not consider the possible congestion occurred in the detailed routing stage, incurring that a congestion-free detailed routing result cannot be generated. As a result, a local congestion model for global routing stage is proposed to translate local congestion information into global routing stage. On the other hand, the global routing flow is also adjusted to handle the overflows induced by local congestion. After adding this local congestion model, global routers can predict the local congestion distribution to avoid it or identify unroutable circuits. Experimental results showed that the proposed method can construct local congestion model in a short time and obtain local congestion information earlier in the global routing stage.
