視訊編碼之研究與軟硬體協同設計;Research on Video Coding and Its Hardware/Software Co-Design

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題名:	視訊編碼之研究與軟硬體協同設計;Research on Video Coding and Its Hardware/Software Co-Design
作者:	蘇聖軒;Su,Sheng-Shuan
貢獻者:	電機工程學系
關鍵詞:	視訊編碼;Video Coding
日期:	2014-07-24
上傳時間:	2014-10-15 17:09:21 (UTC+8)
出版者:	國立中央大學
摘要:	隨著科技的進步，人們對視訊品質及解析度的要求也愈來愈高，從過往的HD或Full HD到如今的4K、8K甚至更高的解析度。在視訊相關應用上，如：影音串流、監控系統、影音儲存以及智慧影像解析，為了保持相對的視訊品質與壓縮率，由VCEG與MPEG共同組成的Joint Video Team (JVT)，於2003年共同發表H.264/AVC視訊壓縮標準，使得高解析度影像可以帶入我們的日常生活中，這兩大工作群組更於2013年共同制定了High Efficiency Video Coding (HEVC)視訊壓縮標準，讓超高解析度影像不再徒留於我們的想像中。以下將分別介紹這兩個近年來的次世代視訊壓縮標準。首先，我們利用Arrow SoC Development Kit作為我們的開發平台，該平台配有ARM Cortex A9 Processor以及 Altera Cyclone V FPGA，藉由此二硬體核心來實現我們的軟硬體設計。我們經過系統分割規劃以及複雜度分析後，將H.264中運算複雜度較高的兩塊模組實現成硬體，分別是Inter Prediction中的Mode Decision及熵編碼的Context-adaptive binary arithmetic coding (CABAC)，以及較易整合於系統的Deblocking Filter。在軟體部分，我們優化了Motion Estimation (ME)傳統的full search及diagonal search，改良成搜尋點數較少、較有效率的Predict Hexagon Search (PHS)。接著，我們提出一個適用於HEVC Inter Prediction中的快速模式決策演算法，優化了需大量運算且不斷遞迴執行的Rate–Distortion Optimization (RDO)決策方式。我們利用JCT-VC推薦的五種不同層級的測試序列以及HEVC Test Model (HM)來評估演算法效能。經由實驗結果得知，此一快速決策演算法最高可減少近50%的運算複雜度，在視訊品質和壓縮率都能維持與HM相差無幾的表現。 ;As the technology progressing, the requirement of video quality and resolution for human being is getting higher and higher, from previous HD or Full HD to nowadays 4K, 8k, or even higher. In the corresponding applications of video, such as: video streaming, surveillance system, video storage, and image analysis. For preserving the relative video quality and compression rate, the Joint Video Team (JVT) established by VCEG and MPEG announced the H.264/AVC video coding standard in 2003. It brings high resolution video into our daily life. Furthermore, these two big studios present the High Efficiency Video Coding (HEVC) standard in 2013; it will lead the ultra-high resolution video to no longer stay in our imagination. The following will introduce these two video coding standards. First of all, we employ the Arrow SoC Development Kit as our development platform; this platform is equipped with ARM Cortex A9 Processor and Altera Cyclone V FPGA. By using these two hard cores to implement our hardware/software co-design. After the system scattering and analysis of computational complexity, we implement the mode decision inside inter prediction and Context-adaptive binary arithmetic coding (CABAC) into hardware together with the deblocking filter. In the software part, we optimize the conventional full search and diagonal search with less searching point and more efficiency Predict Hexagon Search (PHS). Next, we proposed a fast mode decision algorithm in HEVC inter prediction. It optimizes Rate–Distortion Optimization (RDO) which needs the heavy computation and be executed routinely. We evaluate the proposed algorithm by employing five levels of test sequence which is recommended by JCT-VC. According to the experimental results, we can recognize that this fast algorithm reduces about 50% computational complexity, and the video quality and coding efficiency are almost same with HM encoder.
顯示於類別:	[電機工程研究所] 博碩士論文

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