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    题名: 微波毫米波寬頻高效率頻率倍頻器之研製;Design and Analysis of Microwave and Millimeter-Wave Broadband High-Efficiency Frequency Multipliers
    作者: 陳冠宇;Chen,Guan-Yu
    贡献者: 電機工程學系
    关键词: 倍頻器;寬頻;高效率;平衡式;轉導提昇;砷化鎵;矽鍺雙載子互補式金氧半導體;互補式金氧半導體;multiplier;broadband;high-efficiency;balanced;Gm-boosted;GaAs;SiGe BiCMOS;CMOS
    日期: 2014-08-20
    上传时间: 2014-10-15 17:11:06 (UTC+8)
    出版者: 國立中央大學
    摘要: 本博士論文主要提出應用於高頻本地振盪系統中,微波及毫米波寬頻高效率頻率倍頻器(frequency multiplier)之設計與分析。首先提出兩個利用砷化鎵異質接面雙極性電晶體及高速電子遷移率電晶體製程(GaAs HBT-HEMT process)實現之頻率倍頻器。一個以共閘級/共源級場效電晶體對為基本架構的寬頻高效率頻率二倍頻器(frequency doubler),其輸出3 dB操作頻率可達8至30 GHz。利用共閘級/共源級平衡式架構的反相特性可省略平衡至不平衡轉換器(balun)的使用,進而縮小晶片面積並減少設計複雜度。在8 dBm的輸入功率下,此頻率二倍頻器在頻寬內可達到轉換增益高於-4 dB及基頻抑制能力優於13 dB的能力。量測輸出飽和功率大於10 dBm。此頻率二倍頻器與過往發表寬頻頻率倍頻器相比,可達到一極佳優化指數(FOM),其值為25.14。接著提出一個應用在Ka頻段單晶石砷化鎵異質接面雙極性電晶體及高速電子遷移率電晶體之頻率四倍頻器(frequency quadrupler)。此四倍頻器基本架構為利用兩級修正共基極/共源級平衡式頻率倍頻器串接而成。在此製程下,不同的電晶體組合組態均已對直流偏壓、諧波輸出功率、轉換增益及轉換效率探討並做優化設計。為了減少電晶體輸出相位誤差及更進一步改善基頻抑制能力,兩組相移器(phase shifter)被應用在電路之中。實驗顯示,輸入功率為4 dBm時,此四倍頻器在操作頻率為23至30 GHz之間,轉換增益可優於-1 dB。在28 GHz輸出頻率下,轉換增益最高為2.7 dB,轉換效率及功率附加效率分別大於8及3.6%。最大輸出飽和功率大於8.2 dBm。晶片面積為2x1 mm2。
    接著提出一個平衡式砷化鎵異質接面雙極性電晶體及高速電子遷移率電晶體頻率三倍頻器(frequency tripler),3 dB操作頻率為10.2至12.6 GHz。在此電路中,一對共基極/共射極異質接面雙極性電晶體被使用為諧波產生器,以期輸出奇次諧波為反相,偶次諧波為同相。接著利用兩個帶通濾波器來抑制三倍諧波外的其他諧波,增進諧波抑制能力。在輸出使用一個共閘級/共源級主動式平衡至不平衡轉換器將三倍諧波同相相加,提供可能的轉換增益。最後,在輸入端使用一個設計在三倍頻的LC共振器進一步提昇轉換增益。實驗顯示,此三倍頻器的轉換增益為2.8 dB,3 dB頻寬比為21.2%,頻寬內的基頻抑制能力優於47 dB。
    最後介紹兩個使用不同轉導提昇(Gm-boosted)技術的頻率二倍頻器。首先提出一個應用在V頻段90奈米互補式金氧半導體製程(90-nm CMOS process)頻率二倍頻器,其使用技術為主動式共源級轉導提昇技術。當轉導提昇技術使用在頻率倍頻器時,因為輸入電壓擺幅等效提昇,可減少輸入驅動功率,因此有效提昇轉換增益。此頻率二倍頻器可達到-3.3 dB的轉換增益,3 dB頻寬比為26.5 %。輸出頻率為60 GHz時,量測輸出飽和功率大於0.8 dBm。接著,利用0.18微米矽鍺雙載子互補式金氧半導體製程(0.18-um SiGe BiCMOS process),成功實現應用在K頻段雙重轉導提昇差動共基極頻率二倍頻器。雙重轉導提昇技術包含主動式共閘級架構和被動式電容交叉耦合(capacitive cross coupling)技術。主動式共閘級轉導提昇級為增益提昇的主要來源,而被動式電容交叉耦合能在不額外增加直流功耗的情況之下,進一步提昇共閘級轉導提昇級本身的增益。詳細的設計流程均在此體現。共源級轉導提昇級及包含交差耦合電容之共閘級轉導提昇級的電流消耗及頻寬也在此做出比較討論。根據提出的雙重轉導提昇架構,此頻率倍頻器可達到-1.3 dB的轉換增益及30.9%的3 dB頻寬比。輸出頻率為26 GHz時,量測輸出飽和功率大於4.5 dBm。
    ;Several microwave and millimeter-wave broadband high-efficiency frequency multipliers are presented in this dissertation for high frequency local oscillation (LO) systems. Two broadband high-efficiency frequency multipliers are designed in heterojunction bipolar transistor and pseudomorphic high electron-mobility transistor (HBT-HEMT) process. First, an 8 to 30 GHz broadband high efficiency, high output power frequency doubler is presented. A common-gate (CG)/common-source (CS) field effect transistor pair is employed in the balanced doubler. The anti-phase property of CG/CS balanced topology can eliminate the need for the additional balun, thus achieving potentially small chip area and reducing design complexity. With an 8-dBm input power, this work features a conversion gain of better than -4 dB with a fundamental rejection of better than 13 dB over the operation bandwidth. The saturation output power (Psat) is higher than 10 dBm. This work presents excellent figure-of-merit (FOM) of 25.14 as compared to other previously reported broadband doublers. A Ka-band monolithic high efficiency frequency quadrupler using a GaAs HBT-HEMT technology is also presented. The frequency quadrupler is constructed cascading two frequency doublers. The frequency doubler employs a modified common-base (CB)/CS topology to enhance the second harmonic efficiently. The dc bias condition, harmonic output power, conversion gain, and efficiency for variable configurations are investigated. Two phase-shifter networks are used to reduce phase error and improve the fundamental suppression. Between 23 and 30 GHz, the proposed frequency quadrupler features a conversion gain of higher than -1 dB with an input power of 4 dBm. The maximum conversion gain is 2.7 dB at 28 GHz with an efficiency of up to 8% and a power-added efficiency (PAE) of 3.6%. The maximum output Psat is higher than 8.2 dBm. The overall chip size is 2x1 mm2.
    A 10.2-12.6 GHz high conversion gain high harmonic suppression balanced frequency tripler is implemented in GaAs HBT-HEMT process. A pair of CB/common-emitter (CE) HBTs is used to generate in-phase and out-of-phase harmonics. Two band-pass filters (BPFs) are utilized at inter-stage to enhance the harmonic suppression. A CG/CS HEMTs active balun is employed to combine the third harmonic in-phase and provide conversion gain. Furthermore, a LC resonator designed at the third harmonic frequency is employed at the input to enhance the conversion gain. The proposed frequency tripler shows a conversion gain of 2.8 dB, a fractional bandwidth of 21.2%, and a fundamental suppression of higher than 47 dB.
    Two Gm-boosted frequency doublers are presented in chapter 4. First, a V-band 90-nm CMOS frequency doubler using active CS-based Gm-boosted technique is introduced. When the Gm-boosted technique is applied to the frequency multiplier designs, the input driving power reduces due to the boosted input voltage swing. Therefore, the conversion gain can be improved. The proposed frequency doubler exhibits a conversion of -3.3 dB and a fractional bandwidth of 26.5%. At 60-GHz output frequency, the maximum output Psat is higher than 0.8 dBm. A K-band doubly Gm-boosted differential CB frequency doubler using 0.18-um SiGe BiCMOS technology is also presented in this chapter. The doubly Gm-boosted configuration consists of an active CG topology and a passive capacitive cross coupling. The active CG Gm-boosted stage provides gain boosting mainly and the cross-coupled capacitor further boosts the gain of the CG Gm-boosted stage without additional dc power. The design methodology of the frequency doubler using Gm-boosted technique is presented. The comparisons of the current consumption and bandwidth using a CS Gm-boosted stage and a CG Gm-boosted stage with a cross-coupled capacitor are also addressed. Based on the doubly Gm-boosted configuration, the proposed frequency doubler achieves a conversion gain of -1.3 dB and a fractional bandwidth of 30.9%. At 26-GHz output frequency, the maximum output Psat is higher than 4.5 dBm.
    显示于类别:[電機工程研究所] 博碩士論文

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