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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/65834


    Title: 考量功耗與阻抗之CMOS 電壓整流器自動化設計與佈局;Automated CMOS Voltage Rectifier Design and Layout with Power and Impedance Consideration
    Authors: 周芳瑜;Jhou,Fang-Yu
    Contributors: 電機工程學系
    Keywords: 電壓整流器;自動化佈局
    Date: 2014-08-27
    Issue Date: 2014-10-15 17:11:23 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 射頻電路的能量收集(energy harvesting)是近期相當熱門的研究,它可以將環
    境中的能量轉換為電路所需的電源,使電路不需要額外的獨立電源即可運作。在
    能量收集的電路中,整流器(rectifier)扮演著不可或缺的角色,因此,本論文針對狄克森多階整流器的架構,提出一套考量效率與輸入阻抗的自動化設計工具,可
    自動依據使用者輸入的規格,找出符合規格的最佳電路設計,並自動產出相對應
    的電路佈局。與之前的研究相比,本論文最大的特點在於將輸入阻抗納入考量,
    讓使用者可以在效率與面積之間做一個適當的取捨,有效避免設計結束後阻抗匹
    配電路不易設計的情況。
    整套自動化工具包含了電路設計與電路佈局兩個部分,皆可在LINUX 上實
    現,所產生的TCL 佈局批次命令檔,亦可在現有的EDA 工具順利執行,產出正
    確無誤地佈局。從實驗數據的觀察可知,本論文所提出的工具確實可以在非常短
    的時間內設計出符合使用者所給定規格之電路及其佈局,大大縮短了射頻電路上
    繁瑣的設計流程。;For radio frequency (RF) circuits, energy harvesting is one of the hot research topics in recent years. By converting ambient energy into the required electrical energy, the circuit can still perform its functionality without any extra power source. In RF energy harvesting circuits, the most important part is the rectifier circuit. Therefore, this thesis proposes an automated design tool for CMOS multi-stage Dickson rectifiers to generate the required designs from specifications to layout with power and impedance considerations. In this thesis, impedance matching has been taken into consideration to have a proper trade off between area and performance.
    Therefore, it can solve the difficulty in previous approaches to match the impedance after design.
    The proposed automation tool is consisted of two parts, circuit sizing and IC layout, which have been implemented in LINUX already. The generated Tcl layout scripts have been tested in commercial EDA tools and generated the corresponding layout successfully. As demonstrated in the experimental results, this tool is able to
    generate the required circuits and layouts that satisfy all users’ specifications in seconds. This is very helpful to shorten the complicated RF IC design flow.
    Appears in Collections:[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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