| 摘要: | 隨著半導體產業技術的演進，積體電路的元件尺寸越來越小，密度也越來越高。由於操作電壓並沒有隨著降低，造成嚴重散熱問題，為了能夠在低電壓與低功率下操作下仍然擁有好的元件特性，改以高遷移率材料作為通道材料是其中一種解決方式。在所有可能的新材料選項中，三五族化合物半導體被視為最有潛力的材料之一，而銻化物半導體具有低能隙與高遷移率的特性，特別受到矚目。然而缺乏高電洞遷移率之p型元件以及化合物半導體元件與矽基板的整合都是必須要克服的瓶頸。
為了解決上述問題，本研究聚焦於成長砷化銦/銻化鋁量子井高電子遷移率n型場效電晶體以及銻化銦鎵/銻化鋁量子井高電洞遷移率p型場效電晶體於砷化鎵基板上，再將這些結構整合在矽基板上，並製作在矽基板上之砷化銦量子井與銻化銦鎵量子井高遷移率電晶體。
藉由磊晶參數與緩衝層結構調整，此研究在砷化鎵基板上所成長的砷化銦量子井結構，最終可達到室溫下電子遷移率超過27,000 cm2/V•s；銻化銦鎵量子井之電洞遷移率則可超過1,000 cm2/V•s。為了整合這些通道特性良好的電晶體於矽基板上，此研究使用了銻化鋁/銻化鎵以及漸變式砷化鎵/銻砷化鎵/銻化鎵兩種異質結構作為起始緩衝層，並探討其對上層量子井結構特性之影響。實驗結果顯示銻化鋁可以在與矽基板的界面形成刃型差排以釋放應力，這樣的差排不會向上延伸影響量子井，然而卻有大量沿著基板傾斜方向分布的雙晶缺陷(twin)，此缺陷造成量子井的成長不均勻以及載子散射，影響元件特性，除此之外這樣的緩衝層阻值過低，造成多層磊晶平行傳導的現象，影響霍爾效應量測結果。相對地，使用組成漸變式砷化鎵/銻砷化鎵/銻化鎵結構雖然表面粗糙度沒有改善，但是卻可以將雙晶缺陷以及部分差排阻擋在銻砷化鎵/銻化鎵界面以下，使上層之量子井具有良好的載子傳輸特性，並且增加緩衝層的電阻值，抑制平行傳導現象；此研究僅用兩微米厚的緩衝層，其電子遷移率在室溫下即可以達到18,100 cm2/V•s。
類似的組成漸變式砷化鎵/銻砷化鎵/銻化鋁緩衝層也被應用在矽基板上成長高電洞遷移率銻化銦鎵量子井。實驗顯示，雙晶缺陷對於銻化銦鎵量子井電晶體的元件特性的影響並不明顯，藉由量子井成長溫度的調整，量子井的電洞遷移率可高達838 cm2/V•s，這是目前已知在矽基板上磊晶成長三五族p型通道電晶體之最高遷移率。本校辛裕明教授團隊以此磊晶片成功開發出小線寬p型通道電晶體，在0.25微米閘極長度的元件上測得最大電流密度可達81 mA/mm (VGS=-1 V and VDS=3 V)，轉導可達75 mS/mm (VGS=0.15 V，VDS=3 V)。
;Along with the increase in device density of Si-based integrated circuits, power consumption and heat dissipation have become key issues that cannot be ignored any more. Replacing Si with high mobility materials to realize high performance transistors with low operating voltage and power consumption is thus a subject under extensive investigations. Among the materials under investigations, III-V compounds are considered one of the most promising candidates. Sb-based compounds have therefore received a lot of attention due to their high intrinsic carrier mobility and low bandgap. However, high performance p-channel transistors and the integration of Sb-based devices on Si substrates remain challenging. To explore the feasibility of the approach above, this work aims at the growth of high quality n-channel InAs/AlSb quantum-well (QW) and p-channel InGaSb/AlSb QW heterostructure field-effect transistors (HFETs) on GaAs and Si substrates by molecular beam epitaxy.
Through the adjustments in layer structures and growth parameters, InAs/AlSb QW HFETs grown on GaAs substrates show electron mobility greater than 27,000 cm2/V•s at room temperature. As for InGaSb/AlSb QW HFETs grown on GaAs substrates, hole mobility higher than 1,000 cm2/V•s at room temperature has also been achieved.
It is found that the buffer layers employed for the growth of InAs/AlSb QW HFETs on GaAs substrates do not give satisfactory results when used for the growth on Si substrates. In this study, AlSb/GaSb and GaAs/GaAsSb/GaSb are used as the initial buffer layer for the growth on Si substrates and how the buffer layer affect the properties of QW HFETs is explored. In the case of AlSb/GaSb buffer, there occur numerous edge dislocations, which do not propagate to the channel, at the AlSb/Si interface to accommodate the lattice mismatch. This buffer also generates numerous planar defects, i.e. twins, which deteriorate the growth of the InAs channel and the electrical properties of the transistors. Besides, parallel conduction of this buffer layer due to its low resistivity is observed. In contrast, the GaAs/GaAsSb/GaSb buffer layer can effectively block the planar defects at GaAsSb/GaSb interface and suppress parallel conduction of the buffer. As a result, the anisotropic transport behavior is greatly reduced. With an approximately 2 m-thick buffer layer, electron mobility as high as 18,100 cm2/V•s has been achieved on InAs/AlSb QWs grown on Si.
P-channel InGaSb/AlSb QW HFETs grown on Si with GaAs/GaAsSb/GaSb buffer layers are also investigated. The growth temperature of InGaSb/AlSb QW is found to be a key parameter for obtaining high hole mobility. By optimizing the growth temperature and layer structure, room-temperature hole mobility of 838 cm2/V•s with sheet carrier density of 9.5×1011 cm-2 has been reached. It is also found that the effects of twins on the electrical properties of InGaSb/AlSb QW HFETs are unobvious. In collaboration with Professor Yu-Ming Hsin, devices with a gate length of 0.25 m are fabricated and exhibit a maximum drain current of 81 mA/mm and a peak transconductance of 75 mS/mm. |
