可見光通訊技術 ( Visible Light Communication, VLC ) 是目前正在發展中一種傳遞資料的通訊技術。本文以光通訊不對稱剪裁正交分頻多工調變 ( ACO-OFDM ) 做為調變方法並結合扮演未來照明主流的 LED 燈具所發出來的光為媒介，探討室內資料傳輸的通訊技術。 VLC 可使用的頻寬 ( 400THz到790THz )，相較於射頻 ( 3kHz到300GHz ) 大很多，且具有快速脈衝響應。另外，其高度的傳輸安全性、隱蔽性，以及能適應於電磁波干擾環境，亦是它的優點之一。儘管 LED 具有高頻寬及快速脈衝響應的特性，但是傳輸距離的影響及傳輸環境中光的干擾，卻會造成傳送資料在傳遞中遭遇通道效應而產生誤差。因此解決通道所造成的失真，為本篇論文的研究重點。 本論文使用光通訊不對稱剪裁正交分頻多工調變做為調變方法，據以設計可見光通訊的同步以及 DHT-based 等化器。對同步符碼偏移和時脈偏移之估測及補償與等化器通道之估測及資料補償，提出有效解決方法。本論文提出使用哈特利轉換指數型增益和相角之自動增益控制與載波回復頻域等化器 ( AGC-CR ) 電路結合可外部控制增益座標軸數位旋轉計數器電路，以 Matlab 與C 語言模擬，並以 Verilog 硬體描述語言實現電路最後使用 TSMC-90 nm 製程來實現所設計之電路，以驗證所提出之電路設計措施的有效性。 ;Visible Light Communication (VLC) is a developing communications technology for data delivery. This paper uses ACO-OFDM as modulation combining with the light form LED lighting applications, which are likely to become the predominant lighting equipment in the future. The bandwidth that which VLC uses (400THz~790THz) is wider than RF (3kHz~300GHz) and VLC also has a fast impulse response. Other advantages of VLC include high security of transmission and adaptability to Electro Magnetic Interference. However, even though VLC has a wider bandwidth and a fast impulse response, it can be interfered by distance and surrounding light during transmission. Thus, it will cause error during data transmission when channel effects occur. In particular, this paper focuses on solving distortion caused by the channel effects. This paper uses ACO-OFDM as modulation, designing a Visible Light Communication Synchronization and DHT-based Equalizer. Providing an effective solution to symbol boundary detection, and the estimation and compensate of sampling clock offset, and the channel effect detection and data recovering of frequency equalizer. This research proposes combining using Discrete Hartley transform to Auto-gain control and Carrier recovery (AGC-CR) with exponential gain and phase against Modified Gain Control-Coordinate Rotation Digital Computer (MGC-CORDIC). Simulations are done by using Matlab and C language, along with utilized Verilog HDL to design the circuit, and realizing the proposed circuit in TSMC-90nm to verify the performance.
