應用於 5-11 GHz寬頻低雜訊放大器與5 GHz/11 GHz雙頻低雜訊放大器之研製;Implementation on Wideband Low Noise Amplifier for 5-11 GHz and 5 GHz/11 GHz Dual Band Low Noise Amplifier Applications

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题名:	應用於 5-11 GHz寬頻低雜訊放大器與5 GHz/11 GHz雙頻低雜訊放大器之研製;Implementation on Wideband Low Noise Amplifier for 5-11 GHz and 5 GHz/11 GHz Dual Band Low Noise Amplifier Applications
作者:	李忠穎;Li,Chung-Ying
贡献者:	電機工程學系
关键词:	低雜訊放大器;寬頻;雙頻;Low Noise Amplifier;wideband;dualband
日期:	2015-07-28
上传时间:	2015-09-23 14:44:47 (UTC+8)
出版者:	國立中央大學
摘要:	此論文採用tsmcTM CMOS 0.18 μm 製程以及 UMC CMOS 0.18 μm 製程設計5-11 GHz寬頻低雜訊放大器及5 GHz/11 GHz雙頻低雜訊放大器，研究的方向以寬頻、雙頻為設計目標。第一顆電路使用電流再利用的技術使得電路能操作在低功耗條件以及shunt peaking的技術來進行設計，輸入端採用T型匹配加上RC回授來進行匹配。本電路增益為12.67 dB，3-dB頻寬從3.9 GHz-14.7 GHz，雜訊最小值為4.04 dB，P1dB量測結果為-13 dBm，IIP3則為-3 dBm，量測功耗為7.92 mW，晶片面積為1.114×0.769 mm2。第二顆電路使用兩級串聯，第一級採用疊接的架構，第二級採用回授的架構，使用疊接架構的好處在於提升增益及隔離度，為了要減少電感數量，電路使用到三組變壓器的設計。本電路增益為14.5 dB，3-dB頻寬從4.9 GHz-11.3 GHz，雜訊最小值為3.18 dB，P1dB量測結果為-16 dBm，IIP3則為-6 dBm，功耗為6.6 mW，晶片面積為0.83×0.95 mm2。第三顆電路使用兩級串聯且皆為疊接的架構，並且在負載端使用shunt peaking的技術，在輸入以及級間匹配採用變壓器來進行設計，此電路雙頻效果由輸入匹配以及級間帶拒濾波器所造成。本電路增益為15.1 dB/10.7 dB，3-dB頻寬從4.75 GHz-6.15 GHz/ 9.45 GHz-12.4 GHz，P1dB為-18 dBm/-12 dBm，IIP3為-8dBm/-3 dBm分別在5.5 GHz及11 GHz，雜訊最低為4.3 dB/5.8 dB，量測功耗為9.6 mW，晶片面積1.31×0.9795 mm2。 ;The primary target of this thesis is to design wideband and dual band low noise amplifier. There are three different circuit designs which are developed in tsmcTM CMOS 0.18 μm and UMC CMOS 0.18 μm. The first circuit is a wideband LNA which employs current-reused and shunt peaking techniques to reduce the power consumption. The input matching adopts T-type and RC feedback to achieve impedance matching. The proposed LNA achieves a gain of 12.67 dB over a 3-dB bandwidth from 3.9 to 14.7 GHz and a minimum noise figure of 4.04 dB. The measured P1dB is -13 dBm and the IIP3 is -3 dBm. The power consumption of the LNA is 7.92 mW. The chip size is 1.114×0.769mm2. The second circuit is a two-stage wideband low noise amplifier. The first stage used cascade topology to enhance the performance of both gain and isolation. Three transformers instead of individual inductor are used to save the chip area. The proposed LNA achieves a gain of 14.5 dB over a 3-dB bandwidth from 4.9 to 11.3 GHz and a minimum noise figure of 3.18 dB. The measured P1dB is -16 dBm and the IIP3 is -6 dBm. The power consumption is 6.6 mW. The chip size is 0.83×0.95 mm2. The final LNA is a dual band low noise amplifier with cascade and shunt peaking topology. The input and inter stage matching networks are realized by transformers to obtain dual band responses which is a bandstop filter between the two pass bands. The proposed LNA achieves the gains of 15.1 dB/10.7 dB over a 3-dB bandwidths from 4.75 to 6.15 GHz/9.45 to 12.4 GHz. The P1dB of dual band LNA are -18 dBm /-12 dBm and the IIP3 are -8 dBm/-3dBm at 5.5 GHz and 11 GHz. The minimum NFs are 4.3 dB/5.8 dB, respectively. The power consumption is 9.6 mW and the chip size is 1.31×0.9795 mm2.
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