Please use this identifier to cite or link to this item:
|Title: ||生醫類比前端電路與壓控對稱式CMOS擬態電阻設計;An Analog Front-End System of Biosignals Acquisition with CMOS Voltage-Controlled Symmetric Pseudo-Resistors|
|Keywords: ||生醫放大器;三角積分調變器;CMOS擬態電阻;Bioamplifier, Delta-sigma modulator, Pseudo-resistor|
|Issue Date: ||2015-09-23 14:45:06 (UTC+8)|
在弱反轉技術的基礎上，我們設計一可調式壓控CMOS擬態電阻，應用於生醫放大器中可調整其頻寬。可調式壓控CMOS擬態電阻包含操作在弱反轉區PMOS與自動電壓調整電路。此可調整頻寬生醫放大器提供40.2 dB 增益、操作頻寬約9.5 kHz、輸入雜訊從6.3 Hz到9.5 kHz 約 5.2 uVrms、從 250 Hz 到 9.5 kHz 約 5.54 uVrms且只有 10.35-uW 功耗.在此電路中低頻截止頻率可調頻寬範圍為 6.3 Hz 到 600 Hz.
可調增益放大器包含偏壓電路、可調式CMOS擬態電阻、ac 耦合式帶通濾波器、共模回授電路。。在電路實現上，在輸入訊號頻率1 kHz、150 uV輸入振幅下，整體放大器增益為72 dB，而在輸入訊號200 Hz，2 mV的輸入振幅下，放大器增益為58 dB，可調低頻截止點範圍為4 Hz到300 Hz，輸入相關雜訊為3.61 uVrms，整體總諧波失真為60.21 dB，雜訊效率因素(Noise efficiency factor)為4.7。我們使用台積電0.18 uV CMOS 1P6M製程，其晶片面積約佔0.68 mm^2。在1.8 V電源供應下，整體晶片消耗之功率約為55 uW。
三角積分類比數位轉換器主要由三角積分調變器與數位降頻濾波器所組成。本文所設計之電路結合SC-SDM與SO-SDM之優點並將其整合，以低功率與高解析度為其設計標的完成一應用於所有生理訊號量測之三角積分調變器。電路實現上，在訊號頻寬10KHz、128倍超取樣率與±0.1V的輸入振幅下，所設計之二階三角積分調變器訊號雜訊失真比為86.47 dB，有效位元數達到13.97位元且整體晶片消耗之功率為318 uW。最後的量測結果顯示訊號雜訊失真比為77.57 dB，有效位元數為12.59位元。在1.8V電源供應下，整體晶片消耗之功率約392 uW。;As modern medicine advances, the portable bio-medical measurement device has become the favorable trend currently. It is expected that the patient can carry light devices for long-term monitoring the physical conditions. In recent years, the bio-signal measurement devices for various bio-medical applications tend to get minimized in collaboration with wireless transmission capabilities.
The purpose of this thesis is to propose a low noise analog-front-end circuit for bio-signal measurement system comprised by a programable gain amplifier and a SC-SO delta-sigma modulator in order to record different bio-signals like Electronencephalogram (EEG) and Electrocardiography (ECG) signals. While the circuit operates at low frequencies, a tunable pseudo-resistor with a huge resistance is seriously required for an extremely low frequency pole to minimize the non-ideal effects, including DC-offset, flicker noise, on chip design, and the like. The issues of process variation and DC-offset from electrode the pseudo-resistor can therefore be resolved. On the other hand, the input stage MOS of the operation amplifier are designed to operate at the weak-inversion region in order to reduce the power consumption and thermal noise effect and obtain better performance than MOS in saturation. Overall, the AFE circuit aims at low power consumption, low-noise, and high resolution.
In this research, a bio-amplifier that employs a voltage-controlled-pseudo-resistor is designed based on weak-inversion technique to achieve tunable bandwidth and extensive operation voltage range for biomedical applications. Through ultra-high resistance for ac coupling, the versatile pseudo-resistor eliminates the dc offset from electrode-tissue interface. Since the voltage-controlled-pseudo-resistor consists of serial-connected PMOS transistors working at the subthreshold region and an auto-tuning circuit, it promises the constant (time-invariant) control-voltage of the pseudo-resistor. Such bandwidth-tunable bioamplifier is designed in a 0.18-um standard CMOS process, achieving gain at 40.2 dB with 10.35-uW power consumption. In addition, the proposed chip can also be used to develop the proof-of-concept prototype, with operation bandwidth at 9.5 kHz, input-referred noise at 5.2 uVrms from 6.3 Hz to 9.5 kHz, 5.54 uVrms from 250 Hz to 9.5 kHz, and tunable cutoff-frequency from 6.3 Hz to 600 Hz.
A bias circuit, a pseudo-resistor, an ac coupling band-pass filter, and common-mode feedback circuit are included in the VGA circuit. With the input signal at 1 kHz sine wave with 150 uW amplitude, the AFE achieves mid-band gain of 72 dB. In the meantime, when the input signal is 200 Hz sine wave with 2 mV amplitude, the AFE achieves mid-band gain of 58 dB. For the programmable low-cutoff frequency, it ranges from 4 to 300 Hz. Moreover, the input referred noise is 3.61 uVrms, and the THD is 60.2 dB. The circuit is fabricated in the TSMC 0.18-um one-poly six metals CMOS process, and the chip area is 0.68 mm^2. Finally, the simulated power consumption is around 55 uW for 1.8 V power supply.
In this thesis, a delta-sigma A/D converter consists of SDM and decimation filter. The proposed SDM is characterized with the advantages of Switched-Capacitor SDM (SC-SDM) and Switched-OPAMP SDM (SO-SDM). Aiming at low power consumption and high resolution, the SDM is accomplished for all applications of bio-signal measurement. It is found that, with an oversampling ratio (OSR) of 128, and 0.2 Vpp amplitude, the modulator achieves 86.47 dB signal-to-noise and distortion ratio (SNDR), 13.97 effective number of bits (ENOB) , and power consumption 318 uW at 10-kHz signal bandwidth. The measurement results show that signal to noise distortion ratio at 77.57 dB, 12.59 ENOB, and the measured power consumption around 392 uW for 1.8V power supply.
|Appears in Collections:||[電機工程研究所] 博碩士論文|
Files in This Item:
All items in NCUIR are protected by copyright, with all rights reserved.