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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/68862


    Title: 氮化鋁鎵/氮化鎵異質接面場效電晶體動態導通特性受電壓應力劣化之研究;The Study of Dynamic Performance Degradation in AlGaN/GaN HFETs with High Voltage Off-state Stress
    Authors: 廖文甲;Liao,Wen-Chia
    Contributors: 電機工程學系
    Keywords: 氮化鋁鎵/氮化鎵異質接面場效電晶體;動態電阻;電流崩塌;GaN HFETs;Dynamic Ron;Current Collapse
    Date: 2015-07-30
    Issue Date: 2015-09-23 14:45:33 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 近年來的研究指出,具有寬能隙的氮化鎵材料有機會提升功率電晶體的崩潰特性,使其具有較低的導通電阻,且更適合應用於高頻系統之中。然而動態導通電阻的特性限制了目前氮化鎵電晶體的發展。
    所謂的動態導通電阻,是指當電晶體受到電壓應力之後,在導通的瞬間會具有較差的導通特性,造成這樣問題的原因已有大量的研究探討,且被歸因於相當多樣且複雜的因子,這樣複雜的問題,導致嘗試解決元件動態電阻問題時,難以找到關鍵因子以有效地提出解決辦法。
    本論文嘗試提出以一系統化的手法分析造成動態電阻的起因;首先討論虛擬閘極的效應,藉由兩極同步電壓切換的技術,建立元件受電壓應力後的暫態 Id – Vg 曲線,藉此以定義元件臨限電壓隨鬆弛時間的變化,此變化可被進一步的分析是與磊晶層有關的缺陷形式。第二個部分連結了漏電流與動態電阻,結果發現閘極漏電流引發磊晶相關缺陷造成的動態電阻劣化可藉由閘極絕緣層大幅改善。更進一步的,改善閘極絕緣層與氮化鎵材料系統間接面缺陷密度的結構也被提出,藉由使用原子層沉積系統沉積二氧化鋁在經高溫氧化過氮化鋁材料上,可有效降低接面缺陷密度至1.4 × 1012 to 2.6 × 1013 eV-1•cm-3。
    元件在承受高電壓應力後,被離子化缺陷的密度分布狀況可藉由分析暫態電容對電壓的關係得到,結果發現,元件在承受過高電壓應力後,被離子化的缺陷密度與電場分佈有明顯的相依關係;且當電壓應力較低時,被離子化的缺陷多分佈在電場集中處,而當高的電壓應力作用在元件上時,一個廣泛範圍的缺陷會被離子化,導致嚴重的動態電阻裂化。此裂化可藉由優化金屬長板的設計分散集中電場來獲得改善。
    為了解到造成元件動態電阻嚴重裂化的根本原因,三電極同步切換的技術被提出,用以研究元件緩衝層內缺陷與動態電阻裂化的關聯,結果發現,當元件承受汲極電壓應力時,若同時施以正向的基板偏壓將導致動態電阻裂化比例上升,且延長了回復所需要的時間,此趨勢與增大汲極電壓的結果相同,從模擬的結果看來,正向的基板偏壓會壓低緩衝層的導電帶能量,缺陷被填入的機率上升,進而影響動態電阻的裂化行為。
    ;The degradation in dynamic on-state performance is a great concern to limit the application of GaN-based power transistors and is regarded as one of the most critical issues to be solved for high power switching applications. When a GaN power transistor was operated as a high frequency on and off switch, the off-state bias duration serves as a filling pulse and causes an increase in RDS,on.
    A measurement methodology involving the synchronous switching of VG and VD was proposed for determining transient Id-Vg curves after an AlGaN/GaN HFET endures high VDS off-state stress. The measurement results indicated slow electron detrapping behavior. The trap profile was determined as (EC–0.6 eV), an acceptor-like trap was widely observed in the AlGaN/GaN HFETs and some research results have indicated that this trap originates from epitaxial defects. The proposed method is further used to study the influence of the trap in AlGaN/GaN HFETs with different buffer layers: a carbon-doped buffer and an Al0.05Ga0.95N back-barrier layer. Two HFETs demonstrated similar transient behaviors but different trends by enduring various VDS stress level. For a device with a C-doped buffer layer, the amount of threshold voltage shift becomes saturated with increasing VDS stress; however, a device with an Al0.05Ga0.95N back-barrier layer does not. A simulation tool was used to analyze the trap behaviors and close agreement was seen between measured and simulated.
    The correlation between off-state leakage current and dynamic RDS,on transients in AlGaN/GaN HFETs with and without a gate insulator under various stress conditions was also examined. The RDS,on transients in a Schottky-gate HFET (SGHFET) and a metal-insulator-semiconductor HFET (MISHFET) were observed after applying various VDS stress biases. The gate insulator in the MISHFET effectively reduced the electron injection from the gate, thereby mitigating the degradation in dynamic switching performance. However, at relaxation times exceeding 10 ms, additional detrapping occurred in both SGHFET and MISHFET when the applied stress exceeded a critical voltage level, resulting in resistive leakage current build-up and the formation of hot carriers. These high-energy carriers act as ionized traps in the channel or buffer layers, which subsequently caused additional trapping and detrapping to occur in both HFETs during the dynamic switching test conducted.
    Gate insulator is an effective mean to reduce the gate leakage current also alleviate the dynamic degradation. However, additional insulator/semiconductor interface states are introduced and to be considered as another origins to trap electrons. To solve this problem, a AlGaN/GaN heterostructure with in-situ AlN as cap layer is proposed. By depositing ALD-Al2O3 on the proposed structure subjected to high temperature oxidization, the interface state can be reduced and the distribution of Dit is determined to be in the range between 1.4 × 1012 to 2.6 × 1013 eV-1•cm-3, which is an approximately one-order-of-magnitude reduction compared with a structure that is not subjected to the oxidization process.
    The use of field plate can effectively reduce the electric-field strength, so the breakdown voltage can be increased and the dynamic degradation can be alleviated. A measurement methodology involving high-voltage C-V was proposed to determine the trapping profile of a stressed AlGaN/GaN HFET. Comparing the curves between initial and stressed C-V measurements revealed that the transient behavior was dominated by ionized acceptor-like traps, and the trapping profile within the high VDS off-state stressed AlGaN/GaN HFET could be deduced. The measurement results also correlated with the degradation in dynamic RDS,on after the transistor was stressed with similar stress conditions. Based on the correlation the deduced trap profiles and dynamic RDS,on degradation, the location with high electric field that determines the major degradation is determined. Finally, a new source field plate is proposed and demonstrated to improve the dynamic performance degradation.
    Finally, the proposed were applied to systematically study the trapping behavior in an AlGaN/GaN HFET endures high VDS off-state stress. Transient Id-Vg is investigated to study threshold voltage shift (ΔVth) after stress. However, the amount of ΔVth was used to evaluate the degradation caused by injection carriers into the region underneath gate. This methodology only addresses one part of the current-collapse effect. The second methodology, stressed C-V, was used to extract the trap profile between the gate field plate edge and source field plate edge. Based on the correlation between the trap profiles and dynamic RDS,on degradation, the location with high trap density that determines the major degradation is determined. Lastly, a new three-terminals synchronous switching with substrate bias was proposed to study the influence of buffer traps. Based on energy-band lifting simulated from simulation tool and the broader trap profile extracted from stress C-V measurement, the most possible region to trap carriers and cause degradation in dynamic Ron is the buffer layer between the gate field plate edge and source field plate edge after off-state near breakdown stress.
    Appears in Collections:[電機工程研究所] 博碩士論文

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