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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/68909

    Title: 以波動數位濾波器為基礎的類比仿真器之管線化設計及其時間與硬體的最佳化;Timing and Resource Optimization of Pipelined Analog Emulator Based on Wave Digital Filters
    Authors: 葉生元;Yeh,Conan
    Contributors: 電機工程學系
    Keywords: 波動數位濾波器;管線化;時間最佳化;硬體最佳化;Wave Digital Filter;Pipeline;timing optimization;resource optimization
    Date: 2015-08-11
    Issue Date: 2015-09-23 14:46:22 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 波動數位濾波器(wave digital filter)可用數位電路模擬類比元件的行為,而以此為基礎的類比仿真器(analog emulator)使得類比與數位混合訊號(analog and mixed signal, AMS)電路的模擬及驗證變得可行,此類比仿真器在波動數位濾波器的基礎上,將時間域中的電阻,電容,電壓源等元件轉至波動數位域,並使用串聯及並聯關係(配線器)以樹狀結構表示出整個電路,再以波的形式輸入訊號以模擬電路行為。為了降低此類比仿真器的硬體成本並提升效能,本論文中提出了一個對此樹狀結構管線化的方法,並隨著關鍵路徑長度限制,自動設計出限制下硬體最佳化的管線化設計,且此方法設計出之結構在模擬後結果可以看出,本論文所提出的方法確實可以在路徑時間限制下,設計出管線化電路結構,以符合要求並最佳化硬體數量。;Wave Digital Filter (WDF) can simulate analog element with digital circuit. The analog emulator based on WDF makes the simulation and verification of mixed signal circuit feasible. This emulator transforms resistor, capacitor, inductance and resistive voltage source into wave digital domain and connect them with either serial or parallel adaptor to represent circuit architecture.
    In order to reduce this analog emulator’s hardware costs and improve efficiency. This thesis proposes an algorithm to generate pipelined WDF tree-like structure. According to different critical path constrain, the pipelined hardware resource can be optimized by the algorithm. From the simulation results on several cases, the proposed method can generate the required pipelined WDF structure that meets the timing constrains and optimize the hardware resource.
    Appears in Collections:[電機工程研究所] 博碩士論文

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