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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/68939

    Title: CMOS製程相容之複晶矽鍺微致冷元件製作與特性探討;Fabrication and Characterization of CMOS Compatible Poly-Si/SiGe Thermoelectric Microcoolers
    Authors: 周城旭;Jhou,Cheng-Syu
    Contributors: 電機工程學系
    Keywords: 複晶矽;複晶矽鍺;矽鍺;致冷元件;熱電;Poly-Si;Poly-SiGe;SiGe;Thermocooler;cooling
    Date: 2015-08-18
    Issue Date: 2015-09-23 14:47:01 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 矽、鍺材料是目前與積體電路製程相容性最佳的半導體材料之一,具有低成本與高熱穩定度的優勢。將矽鍺材料微型熱電致冷器置放於積體電路中,針對熱點進行有效的降溫,是未來解決電子元件散熱問題的最佳解。本實驗室已製作且探討柱寬100 nm的複晶矽鍺奈米柱陣列之熱導率、電導率等特性,其中鍺莫耳百分比濃度24%之矽鍺奈米柱陣列,於300K之ZT值估算可達0.5。
    本論文研究設計17 × 12 μm2、37 × 32 μm2以及56 × 52 μm2三種面積的複晶矽(Poly-Si)與複晶矽鍺(Poly-Si0.76Ge0.24)柱子(直徑為250 nm/柱高為1 µm)陣列,並重摻雜為P-type (Boron,1 × 1020 cm-3)與N-type (Phosphorus,1 × 1020 cm-3)。再分別以蒸鍍鎳與矽鍺反應形成矽化鎳或矽鍺化鎳以及蒸鍍鋁輔以掀離(lift-off)製程串聯奈米柱底部與頂部,完成P-N對奈米矽鍺柱微型熱電致冷元件。
    分別控制環境溫度於30、60與90 oC,以電流1、3、5、7、9與11 µA驅動元件,探討奈米矽鍺柱陣列面積以及複晶矽鍺內的鍺濃度對於致冷溫度之影響。實驗結果顯示,對於複晶矽柱陣列而言,不論其陣列面積大小、注入方式(N或P-型注入)、注入電流大小或測試環境溫度,皆無明顯之致冷效果,溫度變化皆在測試之誤差變異以內。反觀,複晶矽鍺柱陣列熱電致冷元件,以P-型端注入為例,56 × 52 μm2陣列有明顯的降溫能力,且測試環境溫度愈高(由306090 oC),致冷溫度差愈佳(4713 oC)。在環境溫度90 oC,注入電流11 µA的條件下,最大的致冷溫度可達13oC。中尺寸37 × 32 μm2之複晶矽鍺柱陣列熱電致冷元件,在N-型端注入驅動電流時,也展現良好的致冷能力。尤其是在環境溫度90 oC、驅動電流11 µA時,具有最佳之致冷效果,致冷溫度可達15 oC。此外,在環境溫度90 oC,注入電流11 µA的條件下,不論是以N-型或P-型端注入驅動電流,皆可以發現增加複晶矽鍺柱陣列的面積可以有效提升其致冷能力。
    ;Silicon and germanium are the best semiconductor material choices for the integrated circuit for their material robustness and the fabrication process compatibility. Therefore, placement of SiGe thermoelectric microcoolers into integrated circuits to cool local hot spots is one of the promising, optimal solution to solve the heat problem in the future. Our research group has fabricated and explored the characteristics of thermal conductivity and electrical conductivity for 100 nm-wide poly-SiGe-pillars-array. Extensive experimental results show that 100 nm-wide, poly-SiGe nanopillars array with the Ge mole concentration of 24% possess, the estimated thermoelectric figure of merit (ZT) to up to 0.5 at 300 K.
    In this thesis, we have fabricated poly-Si and poly-Si0.76Ge0.24 P-N pillars (diameter of 250 nm/ height of 1 μm) arrays with various of area size in 17 × 12 μm2, 37 × 32 μm2 and 56 × 52 μm2. P-N pillars were produced by ion implantation of Boron/1 × 1020 cm-3 as P-dopants and Phosphorus/1 × 1020 cm-3 for N-type donors, respectively. Following nickel evaporation and silicidation and rapid-thermal annealing, NiSi/NiSiGe nanocontacts were produced to connect the bottom of N- and P-pillars. Also aluminum top electrodes form by thermal evaporation of aluminum in conjunction with lift-off process were formed to bridge the top of pillars, the P-/N- pair SiGe nanopillar thermoelectric microcooler.
    We systematically investigated effects of the array size and Ge concentration of poly-SiGe nanopillars on cooling capability at test conditions of the environmental temperature at 30, 60 and 90 oC as well as the driving current of 1, 3, 5, 7, 9 and 11 μA, respectively. Experimental results suggest that the poly-Si0.76Ge0.24 thermoelectric cooler with areas size of 37 × 32 µm2 possesses the best of the cooling capability with cooling temperature up to 15 oC for the condition of environmental temperature at 90 oC, and driving current at 11 μA.
    Appears in Collections:[電機工程研究所] 博碩士論文

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