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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/69038

    Title: 應用於邏輯與動態隨機存取記憶體堆疊式三維積體電路之堆疊後測試與良率提升方法;Post-Bond Test and Yield-Enhancement Techniques for Logic-DRAM Stacked ICs
    Authors: 楊維軒;Yang,Wei-Hsuan
    Contributors: 電機工程學系
    Keywords: 三維積體電路;堆疊後測試;良率提升方法;3D IC;Post-Bond test;Yield-Enhancement
    Date: 2015-08-27
    Issue Date: 2015-09-23 15:11:53 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 使用矽穿孔(through silicon via)的三維整合技術是目前被大家公認的積體電路設計技術之一。為了克服記憶體不足,邏輯與動態隨機存取記憶體(DRAM)堆疊式三維整合晶片是一種有效的方法。由於邏輯與動態隨機存取記憶體可能來自不同的製造商,對一個堆疊式三維整合者有效的測試與診斷矽穿孔是很重要的。此外,堆疊過程可能最造成瑕疵(defect)散落。堆疊後的良率提升也是很需要的。
    在本論文的第一部分,我們提出應用於邏輯與動態隨機存取記憶體(DRAM)堆疊式可程式化內建自我測試電路(built-in self-test )。內建自我測試電路產生控制訊號給動態隨機存取記憶體中的類1149.1邊界掃描(boundary scan),還有產生測試樣型(test pattern)去涵蓋(cover)邏輯與動態隨機存取記憶體間矽穿孔的永駐錯誤(stuck-at fault)與開路錯誤(open fault)。我們也提出一個診斷出永駐錯誤與開路錯誤位置的演算法。除此之外,自我測試電路可以產生測試樣品經由邏輯的邊界掃描給動態隨機存取記憶體。對於一個四通道512位元寬輸入輸出動態隨機存取記憶體(wide I/O DRAM),我們的測試和診斷演算法需要4754個時脈週期數。自我測試電路使用TSMC 90nm製程實現的面積為7359.4um2。
    在本論文的第二部分,我們提出一個內建自我修復方法(BISR)來提升三維動態隨機存取記憶體,其中利用了通道間冗餘互相修復方法(inter-channel redundancy),此方法可以提升了冗餘利用率。我們也提出內建冗餘分析(BIRA)演算法來分配冗餘到通道間。模擬實驗可以看出在平均值為6時,我們提出的分法相較於傳統方法提升了20.3%的修復率(repair rate)。對一個32G位元的動態隨機存取記憶體,自我修復電路使用TSMC 90nm製程實現的面積為47880um2。
    ;Three-dimensional (3D) integration technology using through-silicon via (TSV) has been acknowledged as one integrated circuit (IC) design technology. Logic and dynamic random access memory(DRAM) stacked 3D IC is considered as one effective approach for overcoming memory wall.
    Since logic and DRAM dies may come from different sources, effective test and diagnosis method for TSVs are imperative for the 3D IC integrator. Furthermore, the stacking process may induce defects. Post-bond yield-enhancement techniques for DRAM stacks are needed.
    In the first part of this thesis, we propose a programmable built-in self-test (BIST) scheme for logic and DRAM stacked 3D ICs. The BIST can generate control signals for the 1149.1-like bboundary scan in the DRAMdies and test patterns for covering the stuck-at and open faults of TSVs between the DRAM dies and the logic die. Also, a diagnosis test algorithm is proposed to locate the positions of stuck-at and open faults. Furthermore, the BIST can generate the test patterns for
    DRAM dies through the boundary scan in the logic die. The test and diagnosis algorithm needs 4754 clock cycles to locate faults for a four channel 512-bit datawidth wide I/O DRAM. The area of the BIST is only 7359.4 um2 using TSMC 90nm CMOS standard cell library.
    In the second part of this thesis, a post-bond built-in self-repair (BISR) scheme is proposed to enhance the yield of 3D DRAMs by using inter-channel redundancy. The inter-channel redundancy can increase the utilization of redundancies. Built-in redundancy analysis (BIRA) algorithms are also proposed to allocate the inter-die redundancy. Simulation results show that the proposed interchannel redundancy scheme can achieve 20.3% increment of repair rate at most than a typical
    redundancy word architecture when the mean value is 6. The area of BISR is 47880 um2 using TSMC 90nm CMOS standard cell library for a 32G-bit DRAM.
    Appears in Collections:[電機工程研究所] 博碩士論文

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