本論文藉由選擇性氧化複晶矽鍺奈米柱/氮化矽/矽材料的結構，來達到低成本、具自我對準且一體成形之鍺奈米球/二氧化矽/矽鍺合金之金氧半異質結構，並且以此結構做成矽鍺電晶體。之前本實驗室已驗證出此結構的介面缺陷約為3.5-5.5×1011 cm-2eV-1 ，足夠做為元件等級的介面，但目前本實驗室都是藉由濕氧900度來氧化矽鍺柱，形成4-5 nm的二氧化矽以及約10 nm的矽鍺合金層，對現今電晶體來說閘氧化層都已微縮至1 nm以下。所以想透過不同的氧化退火條件，來達到可以控制二氧化矽層的厚度，並且想利用SOI 基板使矽鍺合金層被二氧化矽限制住，讓矽鍺合金層的鍺濃度提升，進而增加矽鍺通道的載子遷移率。 我們做了一系列調變氧化退火條件的實驗，藉由調變氧化時氧流量、矽含量及氧化溫度進而找到最適合我們金氧半電容的條件。發現到當我們降低氧化退火溫度時，可以明顯看到閘介電層厚度有明顯下降的趨勢，且藉由電流-電壓、變頻電容-電壓量測可以看到不只厚度變薄，二氧化矽的品質跟著提升，對我們後續想做的矽鍺電晶體來說，無疑的是一種改善的方法。 ;We demonstrated a unique approach to generate self-organized, self-alignment, and low-cost Ge-nanoball/SiO2/SiGe-shell gate-stacking heterostructures through the selective oxidation of poly-Si0.83Ge0.17 nano-pillars over the Si3N4 buffer layer on the Si substrate, and then would like to realize SiGe MOSFETs based on this designer heterostructure in the near future. It has been previously demonstrated that the interface trap density (Dit) of SiO2/SiGe heterostructure in the designer heterostructure is about 3.5−5.5 × 1011 cm-2eV-1, which is a promising candidate for high-performance Ge MOSFETs. However, 4nm-thick amorphous interfacial oxide layer was generated during thermal oxidation at 900 °C in H2O ambient, which cannot meet the criteria of prevailing CMOS technology with gate oxide less than 1 nm. In this work, we further reduced the thickness of this SiO2 interfacial layer by tuning the oxidation conditions, such as temperature and oxidation ambient. On the other hand, a SOI substrate was also employed to decrease the SiGe-shell thickness and then increase the Ge content in SiGe shell, forming a high-carrier mobility channel. According to a series of experiments with various oxygen fluxes and temperatures in thermal oxidation process as well as different Si substrate to control Si flux, we found the thickness of interfacial SiO2 layer would be significantly reduced with decreasing thermal oxidation/annealing temperature. Meanwhile, gate-oxide quality was also raised as the oxidation temperature decreased, which was confirmed by extensive current-voltage and capacitance-voltage characterizations in MOSC devices. Both results provide great promises for apply the designer gate-stacking heterostructure in Ge MOS applications.
