| 摘要: | 本論文提出應用於正交分頻多工通訊系統中之低複雜度多輸入多輸出偵測器之演算法架構與電路實現。首先根據傳統K最佳演算法中所需之排序運算，我們提出了兩種能夠改善多條候選路徑排序效率之快速排序演算法，分別為平行切割合併法以及平行氣泡排序法以增加排序的效率及縮短排序消耗的時間週期。並且提出改良型K最佳演算法，在不損失錯誤率效能下將傳統K最佳解碼過程中的每層皆需排序修改為每兩層才需排序，以減少排序動作消耗的運算複雜度。接下來以分佈型K最佳演算法為基礎，發展具有高資料吞吐率之高能源效率低複雜度之多輸入多輸出偵測器。由於分佈型K最佳演算法不需要排序動作之優點，結合多層管線式電路架構，能夠達到高資料吞吐量之要求。再結合連續干擾消除演算法，將解碼後段過程中之拜訪節點進一步降低，以達成高能源效率。並且基於模組化管線式電路架構之彈性，能夠在不損失電路利用率及保持相同資料吞吐率下支援2x2、4x4以及8x8之多種天線組態。最後由於傳統K最佳演算法針對不同通道條件均採用相同K值，我們提出一套適應性K值自我調整演算法，能夠依照通道環境的優劣減少不必要的拜訪結點。在解碼過程中並不需要計算通道環境之訊雜比即可快速決定每一層合適的K值。以上提出之演算法依據演算法特性與應用需求，硬體實現架構分別有管線式與迴圈式，其中管線式架構能夠達到高速資料輸出之要求以及高能源效率，並且彈性支援2的冪次多重天線組態。迴圈式架構能夠適用於更複雜的天線組態並享有電路資源的可重複利用彈性，適用於較複雜演算法之實現。在此我們利用CMOS 90奈米製程，實現了三種不同演算法之硬體設計，支援天線數從2x2、4x4、8x8以及2x2至8x8，資料調變可以支援BPSK、QPSK、16-QAM以及64-QAM，K值大小為5、10手動調整以及2、5、10自我適應性調整。;This thesis proposes design and implementation of low-complexity multiple-input multiple-output detectors for orthogonal frequency division multiplexing communication systems. In the conventional K-Best algorithm, sorting operation of Partial Euclidean Distance (PED) values occupies a lot of computing complexity. First, we propose two types of fast sorting algorithms to deal with the large amount of enumerated candidate paths: Parallel Slice Merge Algorithm (PSMA) and Parallel Bubble Slice Sort (PBSS). Furthermore, modified K-Best (MKB) algorithm is proposed to perform sorting operation for every two layers, thanks to the proposed sorting algorithms. The MKB algorithm can reduce the computing complexity of sorting operation in the conventional K-Best algorithm without losing BER performance. Next, by taking the advantage of sorting free characteristic of Distributed K-Best (DKB) algorithm, we develop high throughput MIMO detector with multi-stage pipelined architecture. To further reducing the number of visiting nodes and achieving high power efficiency, we combine DKB algorithm with Successive Interference Cancelling (SIC) algorithm.
By applying pipelined hardware architecture and modular functional blocks, the proposed DKB+SIC MIMO detector can maintain high circuit utilization and constant throughput supporting 2x2, 4x4 and 8x8 antenna configurations.
Finally, we propose an adaptively K-value self-adjusting mechanism to reduce unnecessary visiting nodes, that is, saving computing complexity when channel environment is good.
Without calculating the exact SNR value of the channel, we can rapidly decide the K-value in each decoding layer.
According to the system applications, the proposed algorithms can be implemented into pipelined or iterative hardware architecture. The pipelined circuit can perform high throughput rate with high power efficiency and flexibly support power of two antenna configurations. The iterative circuit architecture can widely adapt various antenna configuration and is suitable for more complicated algorithms. We have implemented three kinds of MIMO detector design in CMOS 90nm process that supports 2x2, 4x4, 8x8 and from 2x2 to 8x8 antenna configurations; multiple data modulations from BPSK, QPSK, 16-QAM to 64-QAM, switch-able 5, 10 K-values and 2, 5, 10 self-adjusting. |
