English  |  正體中文  |  简体中文  |  Items with full text/Total items : 75369/75369 (100%)
Visitors : 25561004      Online Users : 439
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version

    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/69219

    Title: LTE下行鏈路發射機與接收機之FPGA實現;Design and Implementation of LTE Downlink transceiver with FPGA
    Authors: 詹佳維;Chan,Chia-Wei
    Contributors: 通訊工程學系
    Keywords: 接收機;發射機;長期演進技術;LTE;Downlink;OFDMA
    Date: 2015-10-20
    Issue Date: 2015-11-04 17:50:38 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 在第四代通訊技術中長期演進技術(Long Term Evolution,LTE)占有十分重要的地位,並隨著LTE技術的日益成熟出現了改良版的LTE Advanced(LTE-A)。在LTE-A中以多重載波聚合技術、結合多天線MIMO技術,大幅的提升傳輸速度。LTE中的下行鏈路為正交分頻多重存取(Orthogonal Frequency Division Multiple Access,OFDMA)系統,此系統正是由正交分頻多工(Orthogonal Frequency Division Multiplexing,OFDM)演進而來,可使頻譜效益增加。本篇論文中對於LTE訊號的傳輸以軟體模擬進行探討並進一步以硬體方式實現。

    在硬體中以Verilog硬體描述語言設計並實現LTE下行鏈路的發射機與接收機,而平台上使用FPGA(Field Programmable Gate Array)板子實現。發射機訊號處理模組中設計了串列與並列轉換處理器、星座圖映射器、參考訊號與主同步訊號置入器、子載波擺放器、反快速傅利葉轉換器以及循環字首置入器。在接收機方面的模組包括了訊號同步器(包括符元時間、載波頻率)、快速複利葉轉換器、子訊框同步器、通道估測以及通道等化器。;LTE(Long Term Evolution) plays an important role in the fourth generation of mobile phone and mobile communication technology. Moreover, LTE technologies is getting mature enough to develop LTE Advanced(LTE-A) technology. It speeds up transmission by using Carrier Aggregation and MIMO technology. On the downlink transmission, the LTE system uses OFDMA(Orthogonal Frequency Division Multiple Access) technology, which is derived from OFDM(Orthogonal Frequency Division Multiplexing). It can increase spectrum efficiency. In this thesis, we simulated LTE signal transmission with MATLAB software and tabulated the real transceiver with hardware technology.

    In hardware, we use verilog hardware description language to conduct design and implement LTE downlink transceiver. On platform, we use FPGA(Field Programmable Gate Array) board. The transmitter includes parallel-to-serial processor, constellation mapper, reference signal and primary synchronization signal inserter, subcarrier placer, IFFT processor and cyclic prefix inserter. The receiver includes signal synchronizer(includes symbol and subcarrier frequency), FFT processor, subframe synchronizer, channel estimator and channel equalizer.
    Appears in Collections:[通訊工程研究所] 博碩士論文

    Files in This Item:

    File Description SizeFormat

    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 隱私權政策聲明