本篇論文設計應用於無線感測網路之K-頻段開關鍵控發射機與接收機電路，論文包含使用台積電CMOS 0.18 μm製程研製的低消耗功率、寬頻鎖定之達靈頓架構除三與除二注入鎖定除頻器。以及使用台積電CMOS 90 nm製程研製的寬頻低功耗、低雜訊指數之低雜訊放大器，以及K-頻段開關鍵控發射機與接收機。整體電路以低消耗功率為設計目標。 本篇論文第二章提出低消耗功率、寬鎖定寬頻之達靈頓架構除三與除二注入鎖定除頻器。除三之注入鎖定除頻器以達靈頓架構提升電路轉導能力，進而將低消耗功率以及利用差動注入器方式以增強注入電流，達到寬的注入頻寬特性。而除二之注入鎖定除頻器則使用達靈頓架構結合LC共振技術，將更為提升電路轉導能力，更加降低整體電路消耗功率。整體電路性能方面，除三之注入鎖定除頻器具有24.71 GHz至28 GHz操作頻率頻寬，在位移頻率為1 MHz時，其鎖定相位雜訊為-140.35 dBc/Hz；本電路之供應電壓為1.45 V，消耗功率為5.13 mW，整體晶片尺寸為0.77×0.79 mm2。除二之注入鎖定除頻器具有20.5 GHz至22.9 GHz鎖定頻寬，在位移頻率為1 MHz時，其鎖定相位雜訊為-138.3 dBc/Hz；本電路之供應電壓為1.2 V時，消耗功率為1.73 mW，整體晶片尺寸為0.8×0.75 mm2。 第三章介紹一顆寬頻低功耗且低雜訊之低雜訊放大器，使用電流再利用技術達到低消耗功率與高增益的特性，輸入匹配則採用正回授之變壓器技術，可以得最佳雜訊與增益且寬頻的響應，並同時達到縮小晶片面積；另外，為了改善線性度問題採用一顆補償gm3放大器產生一個負的gm3與電流再利用的gm3相消，藉以提升電路的IIP3。在供應電壓為0.8 V，消耗功率為4.76 mW時，電路得到最高增益與最低雜訊分別為11.98 dB與2.83 dB，P1-dB與IIP3分別為-12 dBm與-3.35 dBm，整體FOM1，增益，雜訊指數，頻寬，OIP3.，操作頻率與dc消耗功率提升至79.44與近年來文獻比較有最好的表現，整體晶片尺寸為0.84×0.6 mm2。 第四章介紹一顆應用於無線感測網路之K-頻段開關鍵控發射機電路，為了實現低消耗功率且具寬頻之發射機電路，在設計上使用一個寬頻的12 GHz之壓控振盪器電路，此振盪器使用了新式的負電阻以降低交錯耦合負阻的寄生電容以達到寬頻之設計，再使用操作在Class B的倍頻器以達到最佳功率轉換效率。而功率放大器則採用Class AB之疊接組態來實現，並且在共源級的閘極端輸入調變訊號，以達到較高的隔離度與快速的資料比之發射機性能。本電路之量測結果如下，可調頻率範圍為19 GHz至23.1 GHz，在位移頻率為1 MHz時相位雜訊為-96.17 dBc/Hz，最大輸出功率為2.91 dBm，消耗功率為22.3 mW，最高傳輸資料率為500 Mbps，換算之能量效率為44 pJ/bit，整體晶片面積為0.6 × 0.92 mm2。 第五章介紹一顆應用於無線感測網路之K-頻段開關鍵控接收機電路，此接收機由低雜訊放大器、封包檢測器及中頻可調增益放大器結合補償直流位移器組成。低雜訊放大器採用兩級共源級放大器並使用正迴授放大器，以達節省面積與低消耗功率寬頻設計：於負載為200 Ω時，整體3-dB頻寬為17 GHz至23.4 GHz，最大增益為20.47 dB。為了降低消耗功率與提高解調之靈敏度，採用單轉雙之封包檢測器並偏壓接近臨界電壓。中頻可調增益則採用三級Cherry-Hooper放大器實現，此架構為一級共源級放大器提供高增益。第二級採用並並回授以得到寬的頻寬，整體可調增益範圍為62.6 dB，而3-dB頻寬為100 kHz至1.4 GHz。由於差動輸出具有直流位移問題，此設計加入一組一階低通濾波器與轉導放大器補償直流位準偏移。整體接收機的性能，在供應電壓為1 V，資料率為600 Mbps時，接收機之消耗功率與平均消耗功率分別為9.52 mW與15.86 nW，最低靈敏度為-47.6 dBm，整體晶片面積為1×0.81 mm2。 ;This study develops a K-band On-Off keying (OOK) transmitter and receiver for wireless sensor network (WSN) applications. A divide-by-3 and a divide-by-2 injection locked frequency divider are implemented by Darlington topology to achieve low power and wide locking range in tsmcTM CMOS 0.18 μm process. This study also develops K-band OOK transmitter and receiver that feature the performance of wideband, low power, low noise figure and high data rate in tsmcTM CMOS 90 μm technology. In Chapter 2, the divide-by-two and divide-by-three injection-locked frequency dividers (ILFDs) using Darlington cell in tsmcTM 0.18 µm CMOS process. The Darlington cell has higher transconductance than traditional cross-coupled common source cell for free-running oscillator that reduces the power consumption of ILFDs. Besides, an LC resonance technique is used in the proposed divide-by-two ILFD to achieve lower power consumption and wide locking range. The measured locking range of the proposed divide-by-two ILFD is from 20.5 to 22.9 GHz. And the measured operation range of the divide-by-three ILFD is from 24.71 to 28 GHz. The measured phase noises of two dividers under locked condition are -138.3 and -140.35 dBc/Hz at an offset of 1-MHz when the input referred signals have phase noises of -132.54 and -131.5 dBc/Hz, respectively. The core power consumptions are 1.73 and 5.13 mW with the supply voltages of 1.2 and 1.45 V, and the chip sizes are 0.8 × 0.75 mm2 and 0.77 × 0.79 mm2, respectively. Chapter 3 presents a low-power and wideband CMOS low noise amplifier (LNA) with current-reused and gate-source transformer feedback techniques to obtain simultaneous noise and impedance matching from 14.7 to 26.7 GHz. The LNA also adopts an auxiliary amplifier to cancel the output third-order transconductance for linearity improvement. The LNA is fabricated in tsmcTM 90 nm CMOS technology and achieves a peak gain |S21| of 11.98 dB and a minimum noise figure (NF) of 2.8 dB. The measured input third-intercept point (IIP3) is -3.35 dBm at 17 GHz under dc power of 4.76 mW from a 0.8 V supply voltage. The overall figure-of-merit (FoM1) regarding gain, noise figure, bandwidth, OIP3, operation frequency, and dc power is up to 79.44 which is the highest one among the recently published works. The chip size of the fabricated LNA is 0.84 × 0.6 mm2. Chapter 4 proposes a high energy-efficiency K-band OOK transmitter in tsmcTM 90 nm CMOS technology. The transmitter consists of a wideband voltage control oscillator (VCO), a frequency doubler and a switch-type power amplifier (PA) with a chip area of 0.6 × 0.92 mm2. The VCO adopts a parasitic capacitance reduction technique to enhance the tuning range to 20.5%. The designed transmitter achieves an output power of 3 dBm with a 500 Mbps data rate from 19 to 23.1 GHz at 22.3 mW power consumption. The correspondent energy-efficiency is 44 pJ/bit. Chapter 5 proposes an OOK receiver which is realized in tsmcTM 90 nm CMOS process. The OOK receiver consists of a two-stage wideband LNA, a single-to-differential envelop detector with RC low pass filter and a 62.6 dB three-stage variable gain amplifier (VGA) with DC offset compensation circuit. The OOK receiver achieved a sensitivity of -47.6 dBm at 600 Mbps data rate under a pseudo random binary sequence (PRBS) 29-1 pattern. The receiver consumes a low power of a 9.5 mW which minimum average power is only 15.86 nW at the input power of -47.6 dBm. The chip area including the test pads is 1 × 0.81 mm2.
