電容比值廣泛應用於類比電路設計，例如：切換式電容積分器、類比/數位轉換器。隨著半導體製程的演進，電容比值的精確度受製程系統性變異與隨機性變異的影響越來越大。由並聯單位電容所組成的電容陣列能有效地抑制製程變異造成的電容比值不匹配，並進而延伸出單位電容佈局問題。本論文的貢獻在於連結電容佈局與電容比值變異的關係，並進而提出分割式演算法於電容陣列佈局。本論文證明給定一個電容佈局範圍時，把單位電容擺置於佈局範圍的中心位置時，將能獲得最小的比值變異。運用這個特徵，較大的佈局範圍切割成數個較小的佈局範圍，並為每個切割範圍的中心位置上擺置單位電容，其所產生的佈局不僅快速且擁有共質心、對稱性與均勻分散等佈局法則。最後，當把這項技術運用在二元權重式電容陣列佈局，例如：逐漸趨近式類比數位轉換器，實驗顯示，本論文所提出的二元權重式電容佈局在二元比值變異、電路線性程度效能、佈局產生的時間均明顯優於現階段已提出之電容佈局。;The key performance of many analog integrated circuits, such as switched-capacitor integrator and analog-to-digital converter, are directly related to their accurate capacitance ratios. The accuracy of capacitance ratio is affected by the systematic and random variations of manufacturing processes more significantly when the manufacturing processes continue to shrink. The variation of capacitance ratio, which can be alleviated by paralleling unit capacitors, is then extended to the capacitor array placement problem. This dissertation is devoted to establish the relationship between the capacitor array placement and the capacitance ratio variation, and to propose the partition-based algorithm to form the capacitor array placement. Placing a unit capacitor at the center of a partitioned sub-array can achieve the lowest variations both systematic and random will be proved. Based on the approach to placing unit capacitor at the center of partitioned sub-array, the capacitor array placement is effectively generated and satisfied the coincidence, symmetry, and dispersion rules. Finally, the proposed algorithm is further applied to the placement of a binary-weighted capacitor array, which is used in successive-approximation register (SAR) analog-to-digital converters (ADCs). Experimental results show that the binary-weighted capacitor array placement can achieve less variation on binary-weighted continued ratio, higher linearity performance, and shorter placement generation time than the state-of-the-art.
