| 摘要: | 本論文主要論述高無動態失真範圍低功耗寬頻追蹤保持放大器之研製，內容包含分佈式放大器與追蹤保持放大器兩部分。主要設計目標為寬頻、低功率消耗及高線性度。論文內容包含電路分析、理想原件電路模擬、整體電路模擬、電路佈局圖、量測結果與改進方法等。
分佈式放大器的部分主要會在第二章介紹。其設計原理包含分佈式放大器的基本組成、增加頻寬與高頻增益的方法和兩種負載的形式等。在章節中會有兩個晶片的實作，分別以改良主動式負載與電阻式負載兩種。設計的過程中會論述電晶體的偏壓與電晶體大小的選擇依據。在模擬方面先以理想元件進行初步評估，再來以佈局電路圖為依據，進行整體電路模擬。之後則是量測分析，量測參數主要以小訊號參數、增益1 dB壓縮點的輸出功率(P1dB)與三階擷取點輸出功率(OIP3)為主。在量測結果上，電阻式負載分佈式放大器頻寬約為DC-63 GHz，直流功耗為112.2 mW，平均小訊號增益為12 dB左右。主動式負載分佈式放大器會頻寬為4 ~ 35 GHz，直流功耗為138 mW，平均小訊號增益為11 dB左右。最後會對模擬與量測結果進行討論，針對特性明顯不佳的部分加以修改，並且模擬修改後的電路。
第三章與第四章主要講述開關電容式與開關射極隨偶器兩種不同開關形式之追蹤保持放大器設計分析。在第三章中，追蹤保持電路主要為開關電容式，在設計上使用消除器減少饋通效應，並且使用雜散電晶體減少時脈訊號對保持電位的影響。在前段會先介紹追蹤保持放大器的操作原理與基本組成電路結構，之後則是介紹在設計追蹤保持放大器時會使用到的參數。第四章主要針對於第三章輸出功率較低與設計面積較大的方向進行改進。電路設計上使用修改達靈頓對來增加輸出增益與減少使用電感，達到增加輸出功率與減少佈局面積。兩個章節在電路設計上分為三個部分，分別是輸入緩衝級、輸出緩衝級與開關三個部分。模擬方面會先以理想元件進行評估，再來則使用全波電磁模擬軟體模擬分析佈局對電路設計之影響。之後為量測結果，其中以小訊號S參數、無失真動態範圍與波形圖為主。在量測結果上開關電容式追蹤保持放大器頻寬約為DC-7 GHz，平均增益約為-7 dB，無動態失真範圍在輸入功率為-4 dBm時大於10 dBc，全諧波失真量小於 -10 dBc，消耗直流功率為132 mW。而開關使用射極隨偶器追蹤保持放大器頻寬約為DC-8 GHz，平均增益為-1 dB，無動態失真範圍在輸入功率為-4 dBm時皆大於35 dBc，全諧波失真量小於 -35 dBc，消耗直流功率為84.7 mW。最後兩個設計會針對特性不佳的部分進行修改，並且呈現出改進模擬分析結果。
;This thesis focus on the design and analysis of the high spurious-free dynamic range and low dc power broadband track-and-hold amplifier. The content consists of two distributed amplifiers and two track-and-hold amplifiers. The design goals of the proposed circuits are broadband, high linearity and low dc power consumption. The circuit design, analysis, simulation, and measurement are completely presented in this thesis, and the discussion and conclusion are also addressed for the future works.
Two distributed amplifiers (DAs) are introduced in Chapter 2. To enhance the bandwidth and gain, the DAs are designed sing active and passive loads in the WIN’s 0.15 and 0.25 μm enhancement/depletion-pseudomorphic high-electron mobility transistor (E/D-PHEMT) process, respectively, and some circuit analysis is presented to verify the design methodology. The dc bias and device size selection is addressed with ideal component for the preliminary circuit simulation. The full-wave EM simulator is also adopted to evaluate the layout design. For the experimental results, the small-signal S-parameters, output 1-dB compression point (P1dB) and third-order intercept point (IP3) are completely performed. The measured 3-dB bandwidth of the DA using resistive load is from DC to 63 GHz with an average small-signal gain of 12 dB, and the total DC power consumption is 112 mW. The measured 3-dB bandwidth of the DA using active load is from 4 to 35 GHz with an average small-signal gain of 11 dB, and the DC power consumption is 138 mW.
Two track-and-hold amplifier (THAs) are designed using TSMC 0.18 μm SiGe process in Chapter 3 and 4. The switch capacitor and the switch emitter follower are employed in the track-and-hold stages of the THAs in Chapter 3 and 4, respectively. The introduction and design principle of the THAs are first presented in Chapters. To further reduce the feedthrough during the hold mode, a differential cancellation technique is proposed for the track-and-hold stage designed using switch capacitor. Moreover, the modified Darlington pair is employed to enhance the gain and bandwidth of the THA, and the chip area is also reduced. The full-wave EM simulator is also adopted for the layout designs of the THAs. For the experimental results, the differential small-signal S-parameters, spurious-free dynamic range (SFDR) and time-domain waveform are performed to completely verify the simulations. The measured 3-dB bandwidths of the THAs are both wider than 7 GHz with insertion gains of -7 and -1 dB, respectively. For the THA using switch capacitor with cancellation technique, the measured SFDR and total harmonic distortion (THD) are better than 10 dBc, -10 dBc, respectively, when the input power is -4 dBm. The total DC power consumption is 132 mW. For the THA using switch emitter follower and modified Darlington pair, the SFDR and THD are better than 35 dBc, -35 dBc, respectively, when the input power is -4 dBm. The total DC power consumption is 84.7 mW. |
