應用於心電訊號感測壓縮之低複雜度可變尺寸正交多重匹配追蹤演算法之設計與實作;Low-Complexity Compressed Sensing with Variable Orthogonal Multi-Matching Pursuit and Partially Known Support for ECG Signals

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Title:	應用於心電訊號感測壓縮之低複雜度可變尺寸正交多重匹配追蹤演算法之設計與實作;Low-Complexity Compressed Sensing with Variable Orthogonal Multi-Matching Pursuit and Partially Known Support for ECG Signals
Authors:	鄭翊君,;Cheng,Yih-Chun
Contributors:	電機工程學系
Keywords:	壓縮感測技術;心電訊號;離散小波轉換;正交匹配追蹤演算法;多重正交匹配追蹤演算法;Compressed Sensing (CS);Electrocardiogram (ECG);digital wavelet transform (DWT);orthogonal matching pursuit (OMP);orthogonal multi-matching pursuit (OMMP)
Date:	2016-03-04
Issue Date:	2016-06-04 12:54:50 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文中，我們提出了應用於無線體域網路(Wireless body sensor network)偵測心電訊號(Electrocardiogram, ECG)之低複雜度壓縮感測技術(Compressed Sensing, CS)。我們利用心電訊號在小波域(wavelet domain)上的特性來找出部分已知支持集合(partially known support set, PKS)，以減少遞迴性貪婪還原演算法(greedy algorithm)估測與擴增步驟的運算量與複雜度。接著我們提出了可變尺寸之正交多重匹配追蹤演算法(variable orthogonal multi-matching pursuit, vOMMP)，此演算法結合了正交匹配追蹤演算法(orthogonal matching pursuit, OMP)與多重正交匹配追蹤演算法(orthogonal multi-matching pursuit, OMMP)之優點。正交匹配追蹤演算法對於在遞迴運算之前段過程可確保搜尋到錯誤率極低的支持集合，維持還原的穩定性。而多重正交匹配追蹤演算法可減少遞迴次數且在遞迴運算的後段，能夠更廣泛的搜尋支持元素以補償前遞迴過程中的搜尋失誤，故更能夠有效的提升還原效能。除此之外，針對正交匹配追蹤相關的演算法最為複雜的運算為偽逆矩陣(pseudo inverse)的運算，我們提出了免反矩陣運算的還原方式，利用QR分解來避免反矩陣運算，相較於傳統求解壓縮感測訊號之正交匹配追蹤演算法，不僅有較低的複雜度，還可以有性能上的改善。實作上，我們用台積電90奈米製程實作。晶片面積(chip area)為 3.61〖mm〗^2 且 gate-count為308K。由晶片量測分析結果可知，在操作電壓0.9伏特且操作頻率為12MHz時，功耗為11.7mW。因此，我們的設計符合極高硬體使用效率，且達成WSBN的低功耗需求。;We present low-complexity compressed sensing (CS) techniques for monitoring electrocardiogram (ECG) signals in wireless body sensor network (WBSN). First, we exploit ECG properties in the wavelet domain to extend the partially known support set (PKS) so as to reduce the support augmentation and estimation efforts in the iterative recovery algorithm. Then, variable orthogonal multi-matching pursuit (vOMMP) algorithm is proposed, using orthogonal matching pursuit (OMP) algorithm in the first phase to effectively augment the support set with reliable supports and adopting the orthogonal multi-matching pursuit (OMMP) in the second phase to rescue the missing support. Furthermore, the computation-intensive pseudo-inverse operation for signal reconstruction is simplified by the matrix-inversion-free technique based on QR decomposition. The performance and complexity comparisons manifest the advantages of our proposed techniques. The vOMMP MIF CS decoder is implemented in 90nm CMOS technology. The chip area is 3.61〖mm〗^2 and the gate-count is 308K gates. From the measurement result, the power consumption is 11.7 mW with supporting voltage at 0.9 V and operating clock at 12 MHz. Compared to prior chip implementations, our design shows good hardware efficiency and is suitable for low-energy applications.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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