| 摘要: | 本篇論文所研究之主題為寬頻高速電路-寬頻分佈式放大器之設計並應用於追蹤-保持放大器，以及微波與毫米波主動式集成天線之設計。論文的第二章為使用砷化鎵製程製作之疊接式的分佈式寬頻放大器的分析與設計，使用之砷化鎵製程同時擁有高電子遷移率電晶體與異質接面雙載子電晶體(HBT)，包含了完整的分析模擬與實驗結果。章節中，對於分佈式放大器之增益級，針對使用兩種不同結構之電晶體組合的疊接架構(HEMT-HEMT, HEMT-HBT, HBT-HEMT, 與 HBT-HBT疊接架構)，所能達成的頻寬與增益進行比較與分析，以提升放大器的電路性能。藉由修正的m-導出式網路(m-dervied network)與使用電感提升的方式加入HEMT-HBT疊接式放大器進行設計，有效的加強分佈式放大器的頻寬與增益。在直流偏壓電路的設計上，使電路達到完全的整合在單晶片中，不須另外使用T型偏壓器(Bias-Tee)或使用其他的元件進行偏壓。本章所實作的分佈式放大器達成43.5 GHz的頻寬與8.5 dB的增益，且最大輸出功率1 dB壓縮點為8 dBm。此外，由12.5 Gbps速率的眼圖量測的結果顯示，本章所設計的分佈式放大器具有優良的傳輸品質。本章所設計之分佈式放大器達成了寬頻，具有良好的平坦度，低的群速度延遲，以及優良的傳輸品質。由於其優越的性能和砷化鎵製程具有大量生產的優點，此分佈式放大器適合應用在現代的高速資料通訊上。
在第三章中，將會介紹關於設計追蹤-保持放大器的基本概念。在第四章中，設計了兩個具有高無雜散動態範圍的高速追蹤-保持放大器，使用了先進的互補式金屬氧化物半導體(complementary metal-oxide-semiconductor, CMOS)製程進行設計，同時具有高速、且低功耗的特性。此外，將分佈式放大器的架構應用於追蹤-保持放大器的輸入級，將操作頻寬提升至19.6 GHz。章節中，藉由分析追蹤保持級的線性度與頻寬的分析，進一步提升追蹤保持放大器的無雜散動態範圍與線性度。藉由挑選適合的開關電晶體尺寸，增強其電晶體打開時的頻關以及擁有高的線性度。在輸入緩衝級的分析中，比較了共源極、疊接式、以及分佈式放大器等不同的架構，比較其增益大小與可達成的頻寬。第一個設計的追蹤-保持放大器使用65 nm CMOS製程，使用了串接共源極與疊接放大器架構作為輸入與輸出緩衝級，達成7 GHz的操作頻寬與40.9 dB的無雜散動態範圍。第二個追蹤-保持放大器使用90 nm CMOS製程實現，加入了分佈式放大器做為輸入緩衝級，達成了19 GHz的操作頻率以及44.5 dB的無雜散動態範圍。本章節所製作的追蹤-保持放大器具有寬頻的操作頻寬，高的無雜散動態範圍，高線性度，高速的取樣速率，密集簡潔的晶片面積，相當適合用於手持儀器。
第五章中，設計了兩個毫米波、振盪器型態的主動式集成天線，使用砷化鎵0.15-μm假型高速電子移動率電晶體(pHMET)製程進行實作。第一個主動集成式天線使用差動式振盪器結合平面式八木天線，兩個電路間使用50歐姆阻抗匹配進行設計。第二個主動式集成天線則是將天現改為迴路天線，並且將天線作為振盪器中的電感-電容槽。章節中，針對此類的設計與阻抗匹配方式進行分析與討論。本章設計的兩個主動式集成天線分別操作在69.7與40.7 GHz，其有效全向幅射功率(effective isotropic radiated power, EIRP)分別為-13.2與-2.7 dBm。本章所提出之設計毫米波主動式天線的方式，可進一步應用於簡易的毫米波無線個人區域網路的應用之中。
;Research on the broadband amplifiers, track-and-hold circuits, and active integrated antennas in microwave and millimeter-wave (MMW) are presented in this dissertation. Design and analysis of the broadband cascode distributed amplifiers (DAs) using GaAs heterojunction bipolar transistor (HBT) / high electron mobility transistor (HEMT) process are completely presented with experimented results in Chapter 2. The gain-bandwidth analysis of cascode gain cell is presented using HEMT-HEMT, HEMT-HBT, HBT-HEMT, and HBT-HBT configurations to improve circuit performance. A modified m-derived network and a HEMT-HBT cascode amplifier with inductive peaking technique are proposed to enhance the gain and bandwidth of the DA. The dc bias networks of the DA are fully integrated in a single chip without off-chip bias-T or bias components. The DAs are designed and fabricated achieve a bandwidth from DC to 43.5 GHz with average gain of 8.5 dB, and the Output power 1-dB compression point is 8 dBm. Moreover, the DA is successfully evaluated with an eye diagram measurement up to 12.5 Gbps, and demonstrates good transmission quality. The DAs achieves broad bandwidth, good flatness, low group delay and good transmission quality. The DAs are suitable in the modern high-speed data communications due to the superior performance and the mass-production MMIC process.
The basic concept of the track-and-hold amplifier is introduced in Chapter 3. Two high-speed track-and-hold amplifiers (THAs) with high spurious-free dynamic range (SFDR) are presented in Chapter 4. The THAs are realized in advanced 65 and 90 nm CMOS processes with high speed and low dc power consumption. The DA is employed in the THAs as an input buffer, and the input bandwidth is highly improved up to 19.6 GHz. The analysis of linearity and bandwidth for the track-and-hold stage is presented to improve the SFDR and linearity. The device size of the switch is properly selected to enhance turn-on bandwidth and high linearity. The analysis of input buffer is addressed with common-source, cascode, and distributed gain stages. The first THA is designed using 65 nm CMOS process with common source and cascode stages as input and output buffers, and it demonstrates an input bandwidth of 7 GHz and a SFDR of 40.9 dB. The second THA is designed in 90 nm CMOS process with a DA as input buffer, and it demonstrates an input bandwidth of 19 GHz and a SFDR of 44.5 dB. The proposed THAs feature broad bandwidth, compact chip area, high SFDR, high linearity, and high sampling rate, and they are suitable in the hand-held instruments.
Two MMW oscillation-type active integrated antennas (AIAs) are design and fabricated in the 0.15-μm GaAs pHEMT process presented in Chapter 5. The first AIA is composed of a differential voltage-controlled oscillator (VCO) and a planar-Yagi antenna, the impedance matching between the two components is 50 Ω. For the second AIA design, the antennas is designed using a loop antenna, and also the antenna is designed as an inductance-capacitance (LC) tank of the VCO. The impedance matching between the differential VCO and the loop antenna is addressed in Chapter 5. The operation frequencies of proposed AIAs are in 69.7 and 40.7 GHz, and the effective isotropic radiated powers (EIRPs) of -13.2 dBm and -2.7 dBm, respectively. The proposed methodology is suitable for the simple MMW wireless personal area network applications. |
