| 摘要: | 有鑑於世界各國人口均朝高齡化社會邁進，戰後嬰兒潮逐漸地由第一線生產主力轉化至退休養老年齡。無論是醫療照護、退休後生活規劃輔助，甚至是營養食品的需求都不斷地提升，符合長照性或數位個人醫療秘書的存在有其必要。透過增加生醫電子醫療儀器的多樣量測生理訊號功能、可靠度與降低儀器本身的功耗、儀器體積與重量以及成本，均有利於當今社會的發展趨勢。故本文將以晶片整合且生醫醫療目的為出發點，將精簡化、微型化、超低功耗、多目的性、高可靠度為開發指標以期能做出對社會大眾福祉有助益之研究作品。
本文由兩部分所組成，第一部分探討生醫類比前端低雜訊放大器，其工作頻寬範圍在5 KHz內，涵蓋了腦波圖 (EEG)、心電圖 (ECG)等生理訊號。透過去除前端電極 (Randel′s model)所造成的DC offset所使用的CCIA架構、透過可提供高阻抗性的Pseudo-Resistor以達到極低頻極點與微型化、低功耗且同時具有抑制閃爍雜訊與熱雜訊的電流重複使用技術 (Current-Reusing)，在低雜訊放大器後端的可調增益式放大器 (PGA)使得生醫訊號放大器整體系統，不再僅能使用於單一化的生理訊號，而是多種人體生理訊號量測均可應用。
在第二部分選用了眾多類比數位轉換器中最符合低功耗條件的逐次逼近式類比數位轉換器 (SAR ADCs)，延續第一部分電路將生醫訊號提供類比數位轉換的功能。在架構上使用了單調式切換技術 (Monotonic Capacitor Switching Procedure) 實現一個10位元，每秒一萬次取樣頻率的類比數位轉換器，相對於傳統的切換技術可有效地降低電容式DAC能量損耗達到只需傳統式19%能量的使用。另外一方面單調式切換技術在比較MSB時，可以進行直接比較MSB，整體電容陣列所需的面積只占傳統式的一半，可大幅度降低晶片面積。Sample/Hold採取靴帶式開關 (bootstrapped)的使用，可將輸入訊號與取樣開關的Ron獨立以達到高線性度電路表現。動態比較器因其只有在進行資料轉換時才會作動，可達到節省靜態功率消耗。綜合以上，整體SAR ADCs設計以低功耗為首要目標。
本文的電路設計均使用台積電0.18 μm CMOS 1P6M製程。第一部分生醫類比前端低雜訊放大器，在輸入訊號頻率250 Hz以及1 kHz、輸入震幅500 μ V下，放大器倍率可從35.917 dB到53.979 dB均可有效放大。輸入雜訊為1.811 μ Vrms，整體雜訊效率因素 (Noise efficiency factor)為1.39，其晶片面積 (包含ESD PAD)占1.322 mm2，整體晶片功耗為2.19 μ W。第二部分SAR，在輸入訊號頻率250 Hz，輸入震幅250 mV下，有效位元為9.638 bits，SNDR為60.1969 dB，其整體品質因數FOM為0.55 pJ /conversion-step，晶片面積(包含ESD PAD)占1.33 mm2，整體晶片功耗為2.602 μ W。
;Recent years, long-term care or digital personal healthcare secretary is necessary. By improving the multi-purpose of biomedical instruments, reliability and reducing power consumption, equipment size and cost are conducive to today′s society. Therefore, this thesis will present a biomedical circuit design and describe how to achieve simplification, miniaturization, low power consumption, multi-purpose and high reliability. Finally hope this research will make everyone be better.
This thesis consists of two parts, the first part introduces our research about biomedical analog front-end low-noise amplifier (LNA), which has operational bandwidth of 5 KHz, covering the EEG, ECG and other bio-signals. The CCIA architecture is used to block DC offset from electrode, taking the high impedance of Pseudo-Resistor to achieve miniaturization and extremely low frequency pole. Moreover, the current-reusing technique is used to maintain low power consumption and keep flicker noise and thermal noise to lower level. Behind the main block LNA, a programmable gain amplifier (PGA) is used. Hence not just only one bio-signal can be measured, but a variety of bio-signals measured can be applied.
In the second part, the successive approximation analog-to-digital converter (SAR ADC) is introduced which can meet the low-power consumption requirement. The function of SAR ADCs is converting the LNA analog signal to digital signal. The main idea of SAR ADCs is Monotonic Capacitor Switching Procedure which can effectively reduce energy loss to 19% of conventional architecture. On the other hand, by using monotonic switching procedure which can directly compare MSB, the overall capacitance array occupies only half of the conventional architecture, which can greatly reduce the chip area. The bootstrapped-switch is used to make input signal and sampling switch independent. The Ron of sampling switch will be fixed and make the S/H achieving high linearity. The main part of SAR ADCs is comparator. In this research the dynamic comparator is better for our research. Because the dynamic comparator only works in the conversion phase, by doing so the static power consumption can be saved. Our design achieves a 10-bit SAR ADC, the primary consideration of SAR ADCs design is low power requirement.
These circuits are designed in TSMC 0.18 μm CMOS 1P6M process. The first circuit is LNA, when input signal frequency is 250 Hz and 1 kHz, 500 μV input amplitude, the mid-band gain of analog front-end low-noise amplifier can be programmed from 35.917 dB to 53.979 dB. The post layout simulation shows that the input-referred noise is 1.811 μV rms, the Noise efficiency factor (NEF) is 1.39, the chip area (including ESD PAD) is 1.322 mm2, the overall chip consumes 2.19 μW. The second circuit is the SAR. When input signal frequency is 250 Hz and input amplitude 250mV, ENOB is 9.638 bits, SNDR is 60.1969 dB, the overall merit FOM is 0.55 pJ per conversion-step, the chip area (including ESD PAD) is 1.33 mm2, the overall chip consumes 2.602 μW. |
