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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/72128


    Title: 毫米波注入鎖定振盪器及鎖頻迴路之研究;Research on Millimeter-Wave Injection-Locked Oscillators and Frequency-Locked Loop
    Authors: 詹駿清;Chan,Chun-Ching
    Contributors: 電機工程學系
    Keywords: 鎖頻迴路;注入鎖定;毫米波;除頻器;振盪器;Frequency-locked loop;Injection-locked;Millimeter-wave;Divider;Oscillator
    Date: 2016-07-14
    Issue Date: 2016-10-13 14:27:27 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 現代通訊系統中,低相位雜訊的壓控振盪器是不可或缺的元件,由於高速資料傳輸量的需求,促使我們研究毫米波的通訊系統。本論文主要針對微波注入鎖定技術應用於振盪器及鎖頻迴路,以達到低功耗、低相位雜訊之研究。第二章闡述一個K頻段高除數、頻寬再生式注入鎖定除六除頻器之分析、設計及量測結果。第三章及第四章分別為鎖頻迴路的分析及具鎖頻迴路自對準之次諧波注入鎖定振盪器之電路設計與量測結果。最後,第五章呈現一個使用變壓器耦合結構的次諧波注入鎖定四相位振盪器。本論文的設計均採用台積電提供的90 nm互補式金氧半場效電晶體製程(TSMC 90 nm GUTM CMOS)。
    第二章介紹數種除頻器架構及設計原理,並且提出注入鎖定除六與除五除頻器對鎖定頻寬的理論模型,從理論模型分析得知,鎖定頻寬跟注入器(injector)的元件與注入訊號大小成正比。同時實現一個再生式注入鎖定除六除頻器,量測最大鎖定頻寬為7.1 GHz相當於31.2%比例頻寬,電路直流總功耗為28.8 mW。
    第三章鎖頻迴路之分析,介紹其理論模型架構,提出各個方塊原件的理論模型及轉移函數,利用ADS(advance design system)軟體進行完整模擬分析,能夠有效率的分析系統的開迴路及閉迴路響應。第四章根據第三章提出的分析方法,設計實現一個具鎖頻迴路自對準之K頻段次諧波注入鎖定振盪器,並利用提出的理論模型分析比較各種結構頻率合成器之相位雜訊及抖動量。量測的鎖頻範圍為24到26.1 GHz,各個控制電壓的鎖定範圍約為100 MHz,輸出功率大於-17 dBm。當輸出鎖定頻率為25.3 GHz時,距載波偏移1 MHz的相位雜訊為-114.3 dBc/Hz,抖動量積分範圍由1 kHz到40 MHz為56.6 fs。電路直流總功耗為50.4 mW,和過去文獻比較擁有最佳的FOM指數。
    第五章提出一個具有低直流功耗與寬注入鎖定範圍之V頻段四相位振盪器,藉由使用變壓器耦合的架構。此次提出的注入鎖定三倍頻器具有下列之優點:1) 與過去傳統的注入鎖定次諧波注入鎖定振盪器相比,由於沒有源級退化(source degeneration),交叉耦合對(cross-coupled pair)所產生的負電阻不會減少,所以可以操作在低直流供應電壓與低功耗。2) 藉由適當選擇注入器的偏壓獲得最大化鎖定範圍。3) 利用阻抗轉換降低注入器的寄生電容。與4) 藉由選擇較大的元件尺寸,讓注入器產生更大的三階諧波功率。根據變壓器耦合架構,提出一個鎖定範圍的理論模型,並與實驗結果相互驗證。量測自由(free-running)振盪頻率從56.6到59 GHz,可調頻率範圍為2.4 GHz。在控制電壓為0.6 V、注入功率為4 dBm三分之一輸出頻率時,鎖定範圍為1.2 GHz。當輸出頻率鎖定在56.6 GHz時,在距載波偏移1 MHz的相位雜訊為-126.8 dBc/Hz,抖動量積分範圍由1 kHz到40 MHz為18 fs。最小四相位誤差及振幅誤差分別為0.32°及0.26 dB,電路直流總功耗為19.8 mW。FOM及FOMT分別為-209及-222。
    ;In modern communication systems, a voltage-controlled oscillator (VCO) is an essential building block. Since the demand for high speed data transmission rate is increasing, we were driven to investigate millimeter-wave communication systems. This thesis focuses on the millimeter-wave oscillator and frequency-locked loop (FLL) using an injection-locked technique to achieve low dc power consumption and low phase noise. Analysis, design and measured results for K-band high-division, broadband regenerative injection-locked frequency divider (ILFD) in Chapter 2. Analysis and design of the FLL and the sub-harmonic injection-locked K-band VCO with FLL self-alignment are presented in Chapter 3 and 4, respectively. Finally, a V-band sub-harmonic injection-locked quadrature VCO (SILQVCO) using a transformer coupled (TC) topology are proposed in Chapter 5. All of the designs in this thesis are fabricated using TSMC 90 nm GUTM CMOS process.
    Several frequency dividers and the injection-locked theory are introduced in Chapter 2. The locking range of divide-by-6 and divide-by-5 ILFDs is investigated to obtain the design methodology. From the analysis, the locking range of ILFDs is proportional to the device size of the injectors and the amplitude of the injection signal. The proposed K-band divide-by-6 ILFD features a locking range of 7.1 GHz and a 31.2% fractional bandwidth. The dc power consumption is about 28.8 mW.
    Analysis of the FLL, including the theoretical models, transfer functions and models using ADS (advance design system) software with system setup of each blocks in FLL are proposed in Chapter 3. We can efficiently analyze the opened-loop and closed-loop responses of the FLL system. Based on the FLL design methodology in Chapter 3, a sub-harmonic injection-locked oscillator with frequency-locked loop self-alignment (SILFLL) are presented in Chapter 4. A theoretical model of the SILFLL is proposed, and the calculated phase noise and jitter are presented for the comparison of various topologies frequency synthesizer. The measured locked range of the SILFLL is from 24 to 26.1 GHz, the locking range for each control voltages is about 100 MHz. The measured output power is higher than -17 dBm over the range. When the injection-locked output frequency is 25.3 GHz, the measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -114.3 dBc/Hz and 56.6 fs, respectively. The total dc power consumption is about 50.4 mW, and this work has the best FOM as compared with literatures.
    In Chapter 5, we proposed a V-band wide locking range SILQVCO with low dc power consumption. By using a transformer coupled (TC) topology, the proposed TC-SILQVCO features the following advantages: 1) the negative resistance of the cross-coupled pair is not degraded due to the proposed SILQVCO without source degeneration, and the TC-SILQVCO can be operated in lower dc supply voltage as compared to the conventional SILQVCOs, 2) the dc bias of the injector can be properly designed for maximizing locking range, 3) the parasitic capacitance provided by the injector can be reduced due to the impedance transformation, and 4) the larger device size of the injector can be properly chosen enhancing the third harmonic. A theoretical model of the proposed TC-SILQVCO is also established and it has been carefully verified with the experimental results. The free-running oscillation frequency of the proposed TC-SILQVCO is from 56.6 to 59 GHz with a tuning range of 2.4 GHz. As the control voltage is 0.6 V and the input power is 4 dBm with one-third output frequency, the measured locking range is 1.2 GHz. When the injection-locked output frequency is 56.6 GHz, the measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz~40 MHz) are -126.8 dBc/Hz and 18 fs, respectively. The minimum quadrature phase error and amplitude error are 0.32° and 0.26 dB, respectively. The dc power consumption is 19.8 mW. The FOM and FOMT are -209 and -222, respectively.
    Appears in Collections:[電機工程研究所] 博碩士論文

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