具頻寬校正機制之寬頻三倍頻鎖相迴路設計;A Wide Range Triple-Push Phase-Locked Loop with Bandwidth Calibration

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/72197

Title:	具頻寬校正機制之寬頻三倍頻鎖相迴路設計;A Wide Range Triple-Push Phase-Locked Loop with Bandwidth Calibration
Authors:	徐延慶;Hsu,Yen-Ching
Contributors:	電機工程學系
Keywords:	三倍頻;頻寬校正;寬頻鎖相迴路;Triple-Push;Bandwidth Calibration;Wide Range PLL
Date:	2016-07-25
Issue Date:	2016-10-13 14:31:33 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文提出一個可操作在0.8 GHz ~ 8.1 GHz，並具有頻寬校正機制之寬頻操作鎖相迴路。藉由三推式倍頻技術，將多相位振盪器輸出進行諧波混波後產生三倍頻，此三倍頻器是獨立於鎖相迴路之外，因此不會影響原鎖相迴路迴授系統，但又能擴增三倍的頻率輸出，因此能減緩寬範圍操作所帶來的鎖相迴路迴路頻寬設計困難度。其中在振盪器與三倍頻器的部分使用差動式的電路架構來強化三次諧波能量，並透過外部控制碼來供使用者選擇鎖相迴路輸出頻率，以同一組控制碼調整電荷幫浦之電流以確保迴路穩定性，達到頻寬校正之機制。此外利用高匹配度的電路佈局方式取代其他相位平均的電路技術，不僅可以有效減少多相位訊號之間的不匹配，也不會增加額外的硬體面積與功率消耗。本論文之寬頻操作鎖相迴路使用90 nm CMOS製程實現晶片，供應電壓為1 V，鎖相迴路輸出時脈為0.8 GHz ~ 2.7 GHz，而三倍頻器輸出時脈為2.4 GHz ~ 8.1 GHz，所有頻率的方均根抖動(JitterRMS)表現皆小於5%時脈週期，在頻寬效正的部分，在1 MHz位置的相位雜訊最大的改善量為10 dBc/Hz，此時的輸出頻率為2.7 GHz。整體晶片所佔面積為1.20 mm2，電路所佔面積為0.048 mm2，電路操作在最高頻率時的功率消耗為13.9 mW。 ;A 0.8 ~ 8.1 GHz wide range phase-locked loop (WRPLL) with bandwidth calibration mechanism is proposed. In this thesis, triple-push technique is used to extend the oscillator tuning range without influence the stability of phase-locked loop. Furthermore, it can relieve difficulties effectively in design loop bandwidth for wide range application. For the weakness of the tripler output power, differential structure are used in oscillator and tripler to enhance 3rd harmonic energy. The output swing of tripler is about twice as large as the traditional single-ended structure. The off-chip control signals are used to adjust both divider ratio and charge pump current in order to maintain the bandwidth and stability across the operating range. In a addition, instead of using any other phase averaging techniques, this thesis proposed a highly symmetric layout method to reduce phases mismatch without increase extra area cost. The experiment chip of the proposed WRPLL was implemented with 90 nm CMOS process. The measured output frequency is 0.8 ~ 2.7 GHz for PLL output and 2.4 ~ 8.1 GHz for tripler output at 1.0 V supply voltage with 13.9 mW power consumption at the highest operating frequency. The maximum improvement of phase noise after bandwidth calibration is 10 dBc/Hz at 1 MHz frequency offset at 2.7 GHz output frequency. The full chip area is 1.20 mm2 and the core area is 0.048 mm2.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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