此論文採用tsmcTM CMOS 0.18 μm 製程設計C/X頻段之寬頻低雜訊放大器以及前端接收機，研究的方向以寬頻、低功耗為設計目標。 第一顆電路使用三級串聯之寬頻低雜訊放大器，為了達到寬頻的輸入匹配，第一級使用了共閘級架構，第二級和第三級以提升增益為目標使用了共源極架構，且三級都使用了汲極至源極變壓器回授技術來進行設計，達到降低雜訊以及增益平坦的效果。本電路增益為13.66 dB，3-dB頻寬從7.19 GHz-13 GHz，雜訊最小值為4 dB，P1dB量測結果為-12 dBm，IIP3則為-2.6 dBm，量測功耗為10.7 mW，晶片面積為0.96 × 0.93 mm2。 第二顆電路使用反向放大架構結合電阻回授之寬頻低雜訊放大器，為了減小輸入匹配寬頻的面積使用，第一級採用反向放大架構且將閘極與源極電感整合為變壓器，第二級使用共源極回授架構來節省面積，結合了汲極至源極變壓器回授來達到增益平坦。本電路增益為11.56 dB，3-dB頻寬從4.9 GHz-11.7 GHz，雜訊最小值為3.5 dB，P1dB量測結果為-12 dBm，IIP3則為-1.9 dBm，量測功耗為8.7 mW，晶片面積為0.73 × 0.68 mm2。 第三顆電路為低功耗寬頻直接降頻接收機，接收機電路架構包含寬頻低雜訊放大器、平衡與不平衡轉換變壓器、寬頻電流模態被動混波器、中頻放大器。為了改善雜訊以及功耗，低雜訊放大器另外設計並非採用第一顆電路的架構；平衡與不平衡轉換變壓器採用電感式耦合共振器的技術來達到寬頻且小面積，且不消耗任何功耗。量測結果的電壓轉換增益為30.03 dB，3-dB頻寬從4.5 GHz-11.7 GHz，雙邊帶雜訊指數最小值為9.2 dB，P1dB量測結果為-21 dBm，IIP3為-14.3 dBm，IIP2則為35.7 dBm，在系統電壓1.8 V下功耗為10.96 mW，晶片面積為2.38 × 0.94 mm2。 ;This thesis develops two circuit designs in tsmcTM 0.18 μm CMOS technology. The primary target of the thesis is to design wideband and low power consumption. The first circuit is a wideband low noise amplifier which employs three stage cascade topology. In order to achieve wideband matching, the first stage used common gate topology. Then, the second stage and third stage used common source topology to enhance gain. The circuit adopted the drain to source transformer feedback techniques, and this technique successfully lowered the noise figure and flatted the gain. The proposed LNA achieves a gain of 13.66 dB over a 3-dB bandwidth from 7.19 to 13 GHz with a minimum noise figure (NF) of 4 dB. The measured P1dB is -12 dBm and the IIP3 is -2.6 dBm. The power consumption of the LNA is 10.7 mW. The chip size is 0.96 × 0.93 mm2. The second circuit is a wideband low noise amplifier which employs the inverter type with resistor feedback topology. In order to reduce the area of the input matching network, the first stage used inverter type topology and integrated the gate and source inductor into transformer. Then, the second stage used resistive feedback common source topology to reduce the size and adopted the drain to source transformer feedback techniques to flatted the gain. The proposed LNA achieves a gain of 11.56 dB over a 3-dB bandwidth from 4.9 to 11.7 GHz with a minimum noise figure (NF) of 3.5 dB. The measured P1dB is -12 dBm and the IIP3 is -1.9 dBm. The power consumption of the LNA is 8.7 mW. The chip size is 0.73 × 0.68 mm2.
The third circuit is a low-power and wideband direct conversion receiver. The receiver circuit consists of a wideband low noise amplifier, unbalanced to balanced transformation transformer and wideband current-driven passive mixer and intermediate frequency (IF) amplifier. To improve NF and power consumption performance of the first design circuit, we redesign the low noise amplifier. An inductively coupled resonator were used in the unbalanced to unbalanced transformation transformer design. This approach reduces the size of passive component and achieves wideband performance without consuming DC power. The proposed receiver achieves a voltage conversion gain of 30.03 dB over 4.5 to 11.7 GHz and minimum double-sideband NF of 9.2 dB. The measured P1dB is -21 dBm and the IIP3 is -14.3 dBm. The measured IIP2 is 35.7 dBm. The power consumption of the receiver is 10.96 mW with the supply voltage 1.8 V. The chip size is 2.38 × 0.94 mm2.
